Abstract: In the fabrication of semiconductor integrated circuits, a method is provided for forming a self-supporting silicon mask and a further method is provided for utiliziing such a self-supporting separable silicon mask to perform various masking steps in the integrated circuit fabrication.The mask is formed by forming, at a surface of a planar silicon substrate, a silicon layer having a higher concentration of conductivity-determining impurities than the substrate beneath the layer, applying to selected portions of the other surface of the substrate an etchant which preferentially etches silicon having lower concentrations of conductivity-determining impurities to thus etch out preferentially selected portions of the substrate to form at least one recess extending through the substrate to said silicon layer, and then etching from the surface of said silicon layer opposite the substrate recess to form patterns of openings extending through the silicon layer to said substrate recess.

Abstract: A method for making a high performance bipolar transistor characterized by self-aligned emitter and base regions and minimized base and emitter contact spacing. The disclosed method comprises forming a recessed oxide-isolated structure having opposite conductivity epitaxial layer and substrate. Multiple layered mass of alternating silicon nitride and silicon dioxide layers are placed over the base region and over the collector reach-through region. Polycrystalline silicon is deposited between the mesas. The mesas are undercut-etched to expose the extrinsic base region which is ion implanted. Then, the mesas are removed to expose the emitter and intrinsic base regions as well as the collector reach-through regions. The latter exposed regions are ion implanted appropriately. Contacts are made directly to the emitter and collector reach-through regions and indirectly via the polysilicon to the base region.

Abstract: A method for making a bipolar filamentary pedestal transistor having reduced base-collector capacitance attributable to the elimination of the extrinsic base-collector junction. Silicon is deposited upon a coplanar oxide-silicon surface in which only the top silicon surface of the buried collector pedestal is exposed through the oxide. Epitaxial silicon deposits only over the exposed pedestal surface while polycrystalline silicon deposits over the oxide surface. The polycrystalline silicon is etched away except in the base region. An emitter is formed in the base region and contacts are made to the emitter, base and collector regions.

Abstract: A method for making both shallow and deep recessed oxide isolation trenches in silicon semiconductor substrates. A semiconductor substrate is reactively ion etched through mask apertures defining the deep trench areas and at least the perimeters of the shallow trench areas, the etched trenches are oxidized and partially filled with chemical-vapor-deposited (CVD) oxide. The filling of the trenches is completed with polycrystalline silicon. The excess polycrystalline silicon covering substrate areas other than the deep trench areas is removed down to the underlying CVD oxide.The shallow trench areas are etched next, some of the shallow trench areas connecting with the upper regions of the deep trench areas. The monocrystalline and polycrystalline silicon in the respective shallow trench areas are removed and the remaining silicon is thermally oxidized.

Abstract: A bipolar dual-channel charge-coupled device having a first channel at the surface for storing a first bit stream of minority charge carrier packets and a second channel buried in the bulk for storing a second bit stream of majority charge carrier packets. The two bit streams are transferred along their respective surface and buried channels simultaneously and independently of each other, thereby substantially increasing the bit storage density of the chip.

Abstract: A method for making wide, deep recessed oxide isolation trenches in silicon semiconductor substrates. A semi-conductor substrate is selectively etched to produce a spaced succession of narrow, shallow trenches separated by narrow silicon mesas. Silicon oxide is chemical-vapor-deposited on the horizontal and vertical surfaces of the etched structure to a thickness equalling the width of a desired silicon oxide mask. The mask is used for etching multiple deep trenches in the substrate, the trenches being separated by thin walls of silicon. The thickness of the walls is uniformly equal to and determined by the thickness of the deposited silicon oxide mask.The deposited silicon oxide is reactively ion etched away from the horizontal surfaces, leaving the oxide only on the sidewalls of the shallow trenches. The silicon is deeply etched, using the remaining oxide as a mask.

Abstract: A compact and lightweight power supply particularly suited for use as a high voltage supply capable of switching voltage values in short time. The high voltage output is compared against a desired reference value to produce a difference voltage which is integrated. The integrated difference voltage is converted to recurrent pulses having a corresponding width. The pulses are applied alternately to the opposite ends of a centertapped primary winding of a specially wound transformer characterized by a specially wound secondary winding and an air-gapped E-shaped core linking the primary and secondary windings. The secondary voltage is applied to a voltage multiplier circuit to produce the high voltage output of the power supply.

Abstract: A multiprocessor system is described which allows for the sharing of memories between the individual processors having synchronous memory interfaces. Three processing units are shown by way of example, each processor having its own local, associated memory. Two of the processing units can each access its own memory but not any other memory. The third processing unit can access its own memory as well as the memories associated with the other two processing units. An engine interface adapter interconnects the I/O busses of the processing units. The functions performed by the engine interface adapter can be divided into two principal groups. The first group of functions permits communication between the processors via their I/O busses. The second group of functions permits the aforedescribed sharing of the memory units between the processing units.

Abstract: A method for forming deep dielectric isolation regions of uniform porous silicon dioxide in silicon wafers having 100 face planes. Subcollector regions of one conductivity type are placed in a silicon substrate of opposite conductivity type. The substrate is covered by an epi layer of the opposite conductivity type. Isolation patterns of heavily doped impurity of the substrate conductivity type are thermally migrated along 110 and 110 crystallographic planes deeply and uniformly through the epi layer and into the substrate between the subcollector regions. The doped isolation patterns are converted to porous silicon by anodic treatment, and the porous silicon is converted into porous silicon dioxide by exposure to an appropriate oxidizing atmosphere.

Abstract: Electrically active defects, i.e., current-carrying defects or leakage paths in silicon crystals, are detected by an anodization process. The process selectively etches the crystal surface only where the electrically active defects are located when the anodization parameters are properly selected. Selected surface portions of the silicon structure are exposed to a hydrofluoric acid solution which is maintained at a negative potential with respect to the silicon structure. When the potential difference is set to a proper value, etch pits are formed in the surface of the silicon only at those locations overlying electrically active defects which impact device yield. The defects are observed and counted to provide a basis to predict yield of desired semi-conductor devices to be formed later in the silicon structure.

Abstract: The present invention provides means for sequencing various supply voltages to electronic circuits and devices to thereby protect those circuits and devices from exposure to deleterious voltages. A first transistor switch connects a first voltage source to a first output terminal. A second transistor switch is connected to the control electrode of the first transistor switch. The second transistor switch, when conducting, causes the first transistor switch to conduct. The second transistor switch is turned on by a second voltage source which is connected through a delay circuit to the control electrode of the second transistor switch. The second voltage source also is connected through a diode and capacitor circuit to a second output terminal.

Abstract: A method for producing deeply recessed oxidized regions in silicon. A series of deep trenches are formed in a silicon wafer by a reactive ion etching (RIE) method. In a first species, the trenches are of equal width. A block-off mask is selectively employed during part of the RIE process to produce trenches of unequal depth. The trench walls are thermally oxidized to completely fill in all of the trenches with oxide at the same time. In a second species, the trenches are of equal depth and width and of uniform spacing. In one aspect of the second species, the width of the trenches is equal to the distance between the trenches whereby the thermal oxidation completely fills in the trenches with oxide at the same time that the silicon between the trenches is fully converted to silicon oxide.

Abstract: A memory array comprising a matrix of cells each of which includes a pair of bipolar transistor inverters. The collector loads of the inverters are commonly connected to a first constant voltage buss. The emitters of the transistors are commonly connected through a second resistor to a second constant voltage buss. Separate writing and reading circuits are provided for each cell in the array so that array cells can be written into and read from simultaneously.

Abstract: A parity checking scheme for detecting memory array word line failures whereby all of the data and parity bits of a plurality of bytes sharing the same word line erroneously assume the value "1" or the value "0". When storing data in the array, the data and parity bits comprising each byte are stored directly except for the parity bit of a selected one of the bytes, which parity bit is inverted by a gated inverter circuit before storing. The same gated inverter circuit also inverts the parity bit of the selected byte upon reading the stored data. All of the remaining bits of all of the remaining bytes are read directly. The read bits of each byte are applied to a respective parity checking circuit of the same even or odd parity type as is used in storing the data. The outputs of all of the parity checking circuits are applied to error control logic.

Abstract: A serial digital-to-analog converter using charge-coupled device technology. The converter comprises, in tandem, an input charge source diffusion, an input charge storage gate, a pair of charge splitting gates and an output charge collecting diffusion. The diffusions and the charge storage and the charge splitting gates are separated from each other by respective control gates.

Abstract: A first in - first out auxiliary memory array for storing binary data wherein each member (word) of the array includes a special bit which is used in combination with the special bits of the other members comprising the same member set to form the address of the next member whose data is to be replaced. Each member comprises an identifier field, a data field and the aforementioned special bit. When a member set is addressed, each member of the set is read to determine whether there is a match on the respective identifier field. If there is a match, the data field of the same member is utilized. If there is no match on the identifier field of any member of the addressed set, the main memory is accessed for the necessary replacement information which is to be written into the member which contains the oldest data. The address of the last-named member is determined by the exclusive ORing of the special bits of all the members comprising the given set.

Abstract: A composite shift register timer for controlling a sequence of events occurring over a demand-response interface. The composite shift register comprises a primary shift register and a secondary shift register. The primary shift register is divided into successive portions which are selectively coupled together in successive pairs upon timely receipt of respective response signals. A first binary "1" is inserted into the first portion at the start of a predetermined sequence of events. The first "1" is clocked through to the end of the first portion where it initiates a demand and is stored pending the receipt of a corresponding response. A second binary "1" is clocked through the secondary shift register beginning with the initiation of each demand. The clocking of the second "1" continues until the receipt of a timely response to the initiated demand whereupon the secondary shift register is reset.

Abstract: An NPN transistor, a P channel and an N channel field effect transistor are formed in the same epitaxial layer on a monolithic semiconductor substrate. Subcollector-like areas of one conductivity type are diffused into selected regions of a semiconductor substrate of the opposite conductivity type. Each subcollector-like area comprises two impurities of the same conductivity type but different concentrations and diffusion rates. An epitaxial layer of the same conductivity type as the substrate is grown over the substrate. One of each pair of subcollector impurities outdiffuses completely through the epitaxial layer during the growth of the epitaxial layer and during subsequent heat treatments to define a plurality of isolated pockets of a conductivity type opposite the conductivity type of the surrounding epitaxial layer and substrate. An NPN bipolar transistor and a P channel field effect transistor subsequently are formed in respective isolated pockets.

Abstract: The method for making patterned resist masks having minimum opening dimensions. The mask is prepared initially using standard photo or electron beam lithography techniques to yield the smallest aperture dimensions consistent with the state-of-the-art. Then, the resulting mask is placed within a chamber containing an atmosphere of resist solvent vapor. The vapor is absorbed by the patterned resist mask causing controlled resist reflow which uniformly reduces the dimensions of the resist openings by an amount determined by time, temperature, resist thickness, resist type and solvent used.

Abstract: An inductively coupled oscillator method for inducing eddy currents in a semiconductor PN junction wafer while irradiating said wafer with pulsed light of selected intensity. The oscillator loading due to the pulsed light modulated eddy current losses is monitored and displayed on an oscilloscope in the form of a decay time plot of voltage amplitude, the plot being a function of the pulsed light intensity and the recombination rate of light-induced electrons and holes on each side of the junctions. The leakage characteristics of the junctions which are desired to be measured are one of the factors determining said rate. Leakage characteristic is made the predominent factor by setting the intensity of the pulsed light to a value which produces a nearly straight line decay time plot on the oscilloscope display. The slope of the line then is a measure of the leakage characteristic.