Abstract: A method of making a semiconductor device includes a substrate having a semiconductor layer having a first portion for non-volatile memory and a second portion exclusive of the first portion. A first dielectric layer is formed on the semiconductor layer. A plasma nitridation is performed on the first dielectric layer. A first plurality of nanoclusters is formed over the first portion and a second plurality of nanoclusters over the second portion. The second plurality of nanoclusters is removed. A second dielectric layer is formed over the semiconductor layer. A conductive layer is formed over the second dielectric layer.

Abstract: A method of making a semiconductor device includes a substrate having a semiconductor layer having a first portion for non-volatile memory and a second portion exclusive of the first portion. A first dielectric layer is formed over the semiconductor layer. A first plurality of nanoclusters is formed over the first portion and a second plurality of nanoclusters is formed over the second portion. A layer of nitrided oxide is formed around each nanocluster of the first plurality and the second plurality of nanoclusters. Remote plasma nitridation is performed on the layers of nitrided oxide of the first plurality of nanoclusters. The nanoclusters are removed from the second portion. A second dielectric layer is formed over the semiconductor layer. A conductive layer is formed over the second dielectric layer.

Abstract: A method forms a split gate memory device. A layer of select gate material over a substrate is patterned to form a first sidewall. A sacrificial spacer is formed adjacent to the first sidewall. Nanoclusters are formed over the substrate including on the sacrificial spacer. The sacrificial spacer is removed after the forming the layer of nanoclusters, wherein nanoclusters formed on the sacrificial spacer are removed and other nanoclusters remain. A layer of control gate material is formed over the substrate after the sacrificial spacer is removed. A control gate of a split gate memory device is formed from the layer of control gate material, wherein the control gate is located over remaining nanoclusters.

Abstract: A latch has a first mode in which the latch functions as a dynamic latch and a second mode in which the latch functions as a static latch. The latch has a feedback circuit that in turn has two parallel switchable loads. The first load is responsive to a data input signal of the latch in the first mode and disabled in the second mode. The second load is responsive to a clock signal in the second mode and disabled in the first mode. The switchable loads being in parallel provides for the ability to select the feedback that is better for the particular mode of operation. The first and second switchable loads can be optimized for the particular mode of operation that will use it.

Abstract: A circuit and method efficiently powers a static storage element during a low voltage mode of operation. The static storage element is powered at a first voltage level in an active mode of the static storage element. The static storage element is powered in a low power mode using alternating first and second phases. Powering the static storage element during the first phases in the low power mode includes powering the static storage element at or below a second voltage level, wherein powering the static storage element during the second phases in the low power mode includes powering the static storage element at a higher voltage level than the second voltage level. In another form two modes of low power operation are used where a first mode uses a less power efficient operation than the second mode, but both are more power efficient than a normal power mode.

Abstract: In a processor having an address translation table, a method includes providing a logical address and control signal. When the control signal has a first value, a first physical address is provided corresponding to the logical address, and when the control signal has a second value, a second physical address is provided. The first physical address and the second physical address are stored in at least one valid entry of the address translation table. In one case, the first physical address is stored in a first valid entry having a tag field which matches the logical address and the second physical address is stored in a second valid entry having a tag field which matches the logical address. Alternatively, the first physical address is stored in a first field of a first valid entry and the second physical address is stored in a second field of the first valid entry.

Abstract: A memory cell is programmed by injecting charge into a charge storage layer of the memory cell. A desired programmed charge results in the charge storage layer over an edge portion of a channel region of the memory cell. An undesired programmed charge results in the charge storage layer over an inner portion of the channel region. Charge tunneling is used to substantially remove the undesired programmed charge in the charge storage layer. In one form the memory cell has a substrate having a channel region, a first dielectric layer over the substrate and a charge storage layer over the first dielectric layer. A second dielectric layer over the charge storage layer has a first portion that is thicker than a second portion to selectively control the charge tunneling.

Abstract: An embedded memory system (10) uses an MRAM core (12) and error correction code (ECC) corrector circuitry (20). The ECC corrector circuitry identifies soft memory bit errors which are errors primarily resulting from an MRAM bit not being correctly programmed. The errors are identified and corrected during a read or a write cycle and not necessarily when the memory is in a special test mode. As errors are corrected, the error corrections are counted by an error counter (24) to create a count value. The count value is stored in the MRAM core itself and can later be retrieved and read during a test mode for an indication of how many bit corrections are required for the MRAM core over a period of time. The count value is stored by using an unused portion of a write memory cycle during a read operation.

Abstract: An input voltage circuit comprises an input transistor having a control electrode for receiving a variable input voltage, a voltage detection transistor having a current electrode coupled to a current electrode of the input transistor forming a first node, and a current source coupled to a second current electrode of the voltage detection transistor forming a second node. The input voltage circuit further comprises a variable voltage drop transistor having a first current electrode coupled to the first node, a control electrode coupled to the second node and a second current electrode coupled to an output node, wherein the voltage detection transistor detects a variation in the variable input voltage and provides a signal to the variable voltage drop transistor. The variable voltage drop transistor generates a voltage drop proportional to the variation in the variable input voltage to ensure a substantially constant output at the output node.

Abstract: A technique to speed up the programming of a non-volatile memory device that has a floating body actively removes holes from the floating body that have accumulated after performing hot carrier injection (HCI). The steps of HCI and active hole removal can be alternated until the programming is complete. The active hole removal is faster than passively allowing holes to be removed, which can take milliseconds. The active hole removal can be achieved by reducing the drain voltage to a negative voltage and reducing the gate voltage as well. This results in directly withdrawing the holes from the floating body to the drain. Alternatively, reducing the drain voltage while maintaining current flow stops impact ionization while sub channel current collects the holes. Further alternatively, applying a negative gate voltage causes electrons generated by band to band tunneling and impact ionization near the drain to recombine with holes.

Abstract: A semiconductor device is formed by patterning a semiconductor layer to create a vertical active region and a horizontal active region, wherein the horizontal active region is adjacent the vertical active region. The semiconductor layer overlies an insulating layer. A spacer is formed adjacent the vertical active region and over a portion of the horizontal active region. At least a portion of the horizontal active region is oxidized to form an isolation region. The spacer is removed. A gate dielectric is formed over the vertical active region after removing the spacer. A gate electrode is formed over the gate dielectric. However, forming the spacer is optional.

Abstract: A semiconductor device (10) such as a FinFET transistor of small dimensions is formed in a process that permits substantially uniform ion implanting (32) of a source (14) electrode and a drain (16) electrode adjacent to an intervening gate (18) and channel (23) connected via source/drain extensions (22, 24) which form a fin. At small dimensions, ion implanting may cause irreparable crystal damage to any thin areas of silicon such as the fin area. To permit a high concentration/low resistance source/drain extension, a sacrificial doping layer (28, 30) is formed on the sides of the fin area. Dopants from the sacrificial doping layer are diffused into the source electrode and the drain electrode using heat. Subsequently a substantial portion, or all, of the sacrificial doping layer is removed from the fin.

Abstract: A memory cell is programmed by injecting charge into a charge storage layer of the memory cell. A desired programmed charge results in the charge storage layer over an edge portion of a channel region of the memory cell. An undesired programmed charge results in the charge storage layer over an inner portion of the channel region. Charge tunneling is used to substantially remove the undesired programmed charge in the charge storage layer. In one form the memory cell has a substrate having a channel region, a first dielectric layer over the substrate and a charge storage layer over the first dielectric layer. A second dielectric layer over the charge storage layer has a first portion that is thicker than a second portion to selectively control the charge tunneling.

Abstract: A semiconductor storage device floats the gate of a conventional transistor between two capacitors to store a logic state which can be utilized to store the condition of a circuit such as a latching type circuit such as a flip-flop or register prior to a power down operation to save power. The gate and first terminals of the two capacitors preferably share the same conductive line such as a polysilicon segment. A second transistor and a second set of capacitors store the complementary state of the logic state so that complementary signals are provided for detecting the stored logic state. After the time for power down has ended, the state of the semiconductor storage device made up of the two transistors and four capacitors is sensed, and the detected logic state is loaded back into the latching type circuit.

Abstract: A data processing system (10) has a debug module (26) that selectively generates one or more debug messages that are specific to a Direct Memory Access (DMA) controller device (16) in the system. A control register(70) enables which of the DMA debug messages are provided. The beginning and end of DMA transfer activity is provided including when minor loop iterations start and complete. Latency information indicating system latency between a channel request and actual initiation of the request for each DMA transfer may also be included in a debug message. One of the debug messages provides periodic status of a predetermined DMA channel under control of a control register (80). At least one of the debug messages implements a watchpoint function, such as indicating when a transfer starts or ends. The debug module may be centralized in the system or distributed among each of predetermined system units.

Abstract: A semiconductor device with strain enhancement is formed by providing a semiconductor substrate and an overlying control electrode having a sidewall. An insulating layer is formed adjacent the sidewall of the control electrode. The semiconductor substrate and the control electrode are implanted to form first and second doped current electrode regions, a portion of each of the first and second doped current electrode regions being driven to underlie both the insulating layer and the control electrode in a channel region of the semiconductor device. The first and second doped current electrode regions are removed from the semiconductor substrate except for underneath the control electrode and the insulating layer to respectively form first and second trenches. An insitu doped material containing a different lattice constant relative to the semiconductor substrate is formed within the first and second trenches to function as first and second current electrodes of the semiconductor device.

Abstract: A voltage controlled oscillator (VCO) has a plurality of series-connected inverters. Within each inverter a first transistor has a first current electrode coupled to a first power supply voltage terminal, a second current electrode, a first control electrode coupled to an output terminal of another inverter of the plurality of series-connected inverters, and a second control electrode for receiving a first bias signal. A second transistor has a first current electrode coupled to the second current electrode of the first transistor, a second current electrode coupled to a second power supply voltage terminal, and a first control electrode coupled to the first control electrode of the first transistor. The second control electrode of the first transistor of each inverter receives a same or separate analog control signal to adjust the threshold voltage of the first transistors thereof to affect frequency and phase of the VCO's signal.

Abstract: Each memory cell of an MRAM that uses toggle writing is written by applying to the memory cell a first field, then a combination of the first field and the second field, then the second field. The removal of the second field ultimately completes the writing of the memory cell. The combination of the first field and the second field is known to saturate a portion, the synthetic antiferromagnet (SAF), of the MRAM cell being written. This can result in not knowing which logic state is ultimately written. This is known to be worsened at higher temperatures. To avoid this deleterious saturation, the magnetic field is reduced during the time when both fields are applied. This is achieved by reducing the current that provides these fields from the current that is applied when only one of the fields is applied.

Abstract: A semiconductor package uses various forms of conductive traces that connect to die bond pads via bond wires. In one form, adjacent bond wires are intentionally crossed around midpoints thereof to reduce self-inductance of the conductors and to minimize self-inductance. In another form, bond wires associated with bond pads having intervening, unrelated bond pads are crossed. Additionally, conductive traces are divided into separate sections and electrically connected by crossed jumper wires or bond wires. Any number of separate sections may be formed for each trace, but an even number is preferable. In another form, one trace is continuous and divides a second trace into two or more sections. The multiple sections are connected by an overlying bond wire. Either insulated or non-insulated bond wire may be used.

Abstract: A technique for alleviating the problems of defects caused by stress applied to bond pads (32) includes, prior to actually making an integrated circuit (10), adding dummy metal lines (74, 76) to interconnect layers (18, 22, 26) to increase the metal density of the interconnect layers. These problems are more likely when the interlayer dielectrics (16, 20, 24) between the interconnect layers are of a low-k material. A critical area or force area (64) around and under each bond pad defines an area in which a defect may occur due to a contact made to that bond pad. Any interconnect layer in such a critical area that has a metal density below a certain percentage can be the cause of a defect in the interconnect layers. Any interconnect layer that has a metal density below that percentage in the critical area has dummy metal lines added to it.