Abstract: A method provides an interconnect structure having enhanced structural support when underlying functional metal layers are insulated with a low modulus dielectric. A first metal layer having a plurality of openings overlies the substrate. A first electrically insulating layer overlies the first metal layer. A second metal layer overlies the first electrically insulating layer, the second metal layer having a plurality of openings. An interconnect pad that defines an interconnect pad area overlies the second metal layer. At least a certain amount of the openings in the two metal layers are aligned to improve structural strength of the interconnect structure. The amount of alignment may differ depending upon the application and materials used. A bond wire connection or conductive bump may be used with the interconnect structure.

Abstract: A system (10) and method manages battery (13) power in a wheel module (11) for indicating when air pressure in a tire falls below a recommended value. Tire air pressure is sensed with a pressure sensor (16). Tire air temperature is sensed with a temperature sensor (18). A determination is made whether the air pressure is increasing or decreasing with respect to time. Based upon whether a ratio of the air pressure and the air temperature is increasing, decreasing or remaining constant with respect to time, tire motion is inferred without directly sensing acceleration or movement of the tire. Power management circuitry (14) controls battery power to enable sensing of air pressure and air temperature at measurement intervals that are longer in time when the tire is not in motion.

Abstract: A storage device structure (10) has two bits of storage per control gate (34) and uses source side injection (SSI) to provide lower programming current. A control gate (34) overlies a drain electrode formed by a doped region (22) that is positioned in a semiconductor substrate (12). Two select gates (49 and 50) are implemented with conductive sidewall spacers adjacent to and lateral to the control gate (34). A source doped region (60) is positioned in the semiconductor substrate (12) adjacent to one of the select gates for providing a source of electrons to be injected into a storage layer (42) underlying the control gate. Lower programming results from the SSI method of programming and a compact memory cell size exists.

Abstract: A transistor is formed using a semiconductor substrate and forming a control electrode overlying the semiconductor substrate. A first current electrode is formed within the semiconductor substrate and adjacent the control electrode. The first current electrode has a first predetermined semiconductor material. A second current electrode is formed within the semiconductor substrate and adjacent the control electrode to form a channel within the semiconductor substrate. The second current electrode has a second predetermined semiconductor material that is different from the first predetermined semiconductor material. The first predetermined semiconductor material is chosen to optimize bandgap energy of the first current electrode, and the second predetermined semiconductor material is chosen to optimize strain of the channel.

Abstract: An automatic gain control (AGC) method and circuit (10) within a receiver uses a digital state machine (26) to implement the AGC function. independent from interaction with a host processor (36) and for multiple modulation protocols without duplicating circuitry. Modulation protocol and parameters for any of various gain responses are stored in a register (29). Multiple states, each corresponding to a predetermined range of RF input signal strength, are stored in the register. Each state contains parameters that determine a gain control signal for controlling a variable gain amplifier (16). The states are independent and may be selectively disabled to create asymmetric responses. Within any state, an adaptable number of iterations may be set to implement a different update rate or step size after a predetermined number of closed loop gain change iterations has not resulted in a transition to a state that represents a desired output gain.

Abstract: A circuit implements a method to adjust input/output (I/O) characteristics of an I/O pad circuit (10) depending upon which value of an I/O supply voltage is used within a range of supply voltages. An I/O supply voltage being supplied to the pad circuit is detected by detecting (18, 20) its value relative to a known reference (16). Portions of the I/O pad circuit are selectively enabled in response to the detected I/O supply voltage. By selecting the ratio of P-channel and N-channel transistors, physical characteristics of the circuit are controlled. Examples of the controlled physical characteristics include slew rate, signal rise and fall times, and duty cycle control which is controlled by forcing all rising and falling edges to have a midpoint at the same point in time. Therefore a same I/O pad circuit may be optimally used in numerous applications regardless of the supply voltage value.

Abstract: A magnetoresistive random access memory (MRAM) (900) that is susceptible to a residual magnetic field is compensated during a write operation. A first magnetic field (208) is applied to a memory cell during a first time period, the first magnetic field having a first direction (y) and a first magnitude. A second magnetic field (212) is applied to the memory cell during a second time period and having a second direction (x) and a second magnitude. A third magnetic field (702) is applied to the memory cell during a third time period, wherein the third time period overlaps at least a portion of the second time period, the third magnetic field having a third direction (?y) which is approximately opposite to the first direction of the first magnetic field. Currents are selectively applied through conductors in the memory cell to apply the three magnetic fields.

Abstract: A one time programmable (OTP) memory has two-bit cells for increasing density. Each cell has two select transistors and a programmable transistor in series between the two select transistors. The programmable transistor has two independent storage locations. One is between the gate and a first source/drain region and the second is between the gate and a second source/drain region. The storage locations are portions of the gate dielectric where the sources or drains overlap the gate and are independently programmed by selectively passing a programming current through them. The programming current is of sufficient magnitude and duration to permanently reduce the impedance by more than three orders of magnitude of the storage locations to be programmed. The programming current is limited in magnitude to avoid damage to other circuit elements and is preferably induced at least in part by applying a negative voltage to the gate of the programming transistor.

Abstract: A storage device and a method in the storage element, where the storage element has a first data storage node and a second data storage node and where the first data storage node is coupled to a bit line via a first pass transistor and where the second data storage node is coupled to a complementary bit line via a second pass transistor, is provided. The method includes performing a clear operation on the first data storage node and the second data storage node by providing a clear signal to a first clear transistor coupled to the first data storage node and a second clear transistor coupled to the second data storage node.

Abstract: Two or more semiconductor packages are stacked with an intervening element that is positioned between within an area surrounded by conductive bumps of a bottom surface of the overlying package. Different shapes of the intervening element are used depending upon how many sides of the bottom surface have conductive bumps. In one form the intervening element extends laterally from the stack and is bent downward to contact or extend through an underlying substrate. Contact to the intervening element at the backside of the substrate may be made. In another form the intervening element is bent upward for enhancing thermal properties. The intervening element is adhesive to prevent non-destructive removal of the packages thereby adding increased security for information contained within the packages. Selective electrical shielding between packages is also provided.

Abstract: A method for removing nanoclusters from a semiconductor device includes etching a selected portion of an insulating layer, flowing a reducing gas over the semiconductor device at a temperature in a range of 400–900 degrees Celsius, and flowing a gas comprising halogen over the semiconductor device at a temperature in a range of 400–900 degrees Celsius. In another form, a method for removing the nanoclusters includes implanting germanium or nitrogen into the nanociusters, etching a selected portion of the insulating layer using a dry etch process, and removing the layer of nanoclusters using a wet etch process that is selective to an insulating layer.

Abstract: A crossbar switch (12) arbitrates for access from multiple bus masters (14, 16, 18, 20 and 22) to multiple addressed slave ports (3 and 4) that have overlapping address ranges. In one form, the address ranges are the same address range. The crossbar switch (12) uses shared slave port control circuitry (48), configuration registers (46) and slave port arbiter logic (34, 36, 38, 40, 42 and 44) to arbitrate for access when all the addressed ports are busy. A determination is made as to whether new access requests are higher or lower in priority than existing accesses. A determination on where to direct a new access request is made based upon a prediction of which of certain multiple accesses will complete first based on various factors including the number of data beats requested as well as wait state information. In one mode, the wait state information is determined dynamically.

Abstract: An integrated circuit is formed by identifying multiple regions, each having transistors that have a gate oxide thickness that differs between the multiple regions. One of the regions includes transistors having a nanocluster layer and another of the regions includes transistors with a thin gate oxide used for logic functions. Formation of the gate oxides of the transistors is sequenced based upon the gate oxide thickness and function of the transistors. Thin gate oxides for at least one region of transistors are formed after the formation of gate oxides for the region including the transistors having the nanocluster layer.

Abstract: An adjustable logic circuit includes a pulse filter and delay circuit, a state machine and combinational logic circuit, and a data strobe generation circuit. The pulse filter and delay circuit is operative to read an adjustable configuration value and, based thereon, to implement a delay between an internal clock and both a data signal and a data strobe signal, the delay being a fraction of a clock period. The state machine and combinational logic circuit are operative to select a data value from a plurality of data values, and to provide a data signal based upon the data value. The data strobe generation circuit is operative to provide the data strobe signal at a time when both the data signal is valid and the delay is compatible with a predetermined external device.

Abstract: An electroless metal deposition process to make a semiconductor device uses a plating bath solution having a reducing agent. A sample of the bath solution is taken and the pH of the sample is increased. The hydrogen evolved from the sample is measured. The hydrogen evolved is used to determine the concentration of the reducing agent present in the sample. Based on the determined reducing agent concentration, the plating bath solution is modified.

Abstract: A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.

Abstract: A memory controller and method thereof configures a prefetch buffer dynamically for interfacing between multiple bus masters of different burst support and multiple memories having different characteristics. A line size of at least a portion of the prefetch buffer is modified based upon the memory controller receiving a read request from one of the bus masters. An adaptive method to optimally replace prefetch buffer lines uses prioritized status field information to determine which buffer line to replace.

Abstract: A storage device structure (10) has two bits of storage per control gate (34) and uses source side injection (SSI) to provide lower programming current. A control gate (34) overlies a drain electrode formed by a doped region (22) that is positioned in a semiconductor substrate (12). Two select gates (49 and 50) are implemented with conductive sidewall spacers adjacent to and lateral to the control gate (34). A source doped region (60) is positioned in the semiconductor substrate (12) adjacent to one of the select gates for providing a source of electrons to be injected into a storage layer (42) underlying the control gate. Lower programming results from the SSI method of programming and a compact memory cell size exists.

Abstract: A semiconductor (10) has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor (75, 77, 79), that are connected by a via or conductive region (52) and interconnect (68, 99). The via or conductive region (52) contacts a bottom surface of a diffusion or source region (22) of the transistor and contacts a first (75) of the capacitor electrodes. A laterally positioned vertical via (32, 54, 68) and interconnect (99) contacts a second (79) of the capacitor electrodes. A metal interconnect or conductive material (68) may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor.

Abstract: A transistor (10) overlies a substrate (12) and has a plurality of overlying channels (72, 74, 76) that are formed in a stacked arrangement. A continuous gate (60) material surrounds each of the channels. Each of the channels is coupled to source and drain electrodes (S/D) to provide increased channel surface area in a same area that a single channel structure is conventionally implemented. A vertical channel dimension between two regions of the gate (60) are controlled by a growth process as opposed to lithographical or spacer formation techniques. The gate is adjacent all sides of the multiple overlying channels. Each channel is formed by growth from a common seed layer and the source and drain electrodes and the channels are formed of a substantially homogenous crystal lattice.