Abstract: A basic tree construction, from which differential cascode voltage switch (DCVS) circuits having variable logic personality can be formed, contains n (>2) rows of differentially associated semiconductor device pairs spanned by n pairs of complementary input conductor leads, and a load circuit coupled to drain terminals of devices in the nth row. The nth row contains 2 device pairs and each other row contains 2.sup.i-1 device pairs (i=1, 2, . . . , n-1). Connections between source and drain terminals of devices in successive rows are predefined from the 1st to the n-1st row and variably definable between the n-1st and nth rows. Connections between input conductors and device gate terminals are predefined in each row other than the nth row, and variably definable in the nth row. Upon selectively defining a set of variable connections relative to the n-1st and nth rows the logic personality of the tree is selected to conform to any one of all possible functions of n variables.

Abstract: The present off/on delay circuit operates within the power supply of a microcomputer system to interrupt transfer of regulated DC voltage to the system microcomputer and attachments in respect to indications of power disturbance and system switch status produced in the supply. Upon termination of such indications, this circuit selectively delays reappearance of regulated DC voltage to the level required for system operation so that whenever the microcomputer resets, the attachments must also reset; thereby preventing lockout impasses in the system rebooting process. The circuit operates in response to a plurality of DC voltage indications in the power supply, including at least an indication distinguishing the state of AC source power as either good or bad, and an indication distinguishing the state of a manually operable system power switch as either on or off.

Abstract: A single chip integrated data link control (IDLC) device provides full duplex data throughput and versatile protocol adaptation between variably configured time channels on a high speed TDM digital link (e.g. T-1 or T-3 line) and a host data processing system. The device can handle multiple channels of voice and varied protocol data traffic, and thereby is suited for use in primary rate ISDN (Integrated Services Digital Network) applications. Synchronous and asynchronous special purpose logic sections in the device respectively interface with the network and a bus extending to external processing systems. Logic in the synchronous section forms plural-stage receive and transmit processing pipelines relative to the network interface.

Abstract: In a computer system accessible via a keyboard--in which the keyboard and system are supposed to reset automatically in reaction to power outages or other disturbances lasting for longer than a first period of time, in which the keyboard and system are generally unaffected by power outages or other disturbances lasting for less than a second period of time less than said first period, and in which lockouts can occur during system power outages or other disturbances lasting for a time greater than said second period and less than said first period--an anti-lockout circuit is interposed between a DC low voltage output port of the system and a DC voltage input port of the keyboard. This circuit is powered by the low DC voltage appearing at said output port and operates in response to small changes in that voltage to switchably interrupt transfer of that voltage to the keyboard input port.

Abstract: A data processing system includes a planar board having a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets or slots, each adapted to receive a selected one of a plurality of different and/or similar option cards. each card contains (or is connected to) and controls a respective peripheral device; and each card is pre-wired with an ID value corresponding to its card type. Software programmable option registers on each card store parameters such as designated default (or alternate) address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in slot positions in main memory, one position being assigned to each slot on the board. Each slot position is adapted to hold the parameters associated with the card inserted in its respective slot and the card ID value.

Abstract: A dual digital signal processor (DSP) provides real time links between multiple time division channels of a digital carrier system (e.g. T-1) and a host data processor. Operating only on digital signals, internally and at its interfaces to the carrier and host systems, the DSP exchanges data and control signalling information with the carrier system and data and control information with the most processor, converting the data in passage to different digital forms. At the interface to the carrier system, signals are received and transmitted in a form adapted to diverse terminal equipment of users remotely linked to the carrier system via the switched public network. At the host interface, signals are transferred and received in a form suited to the data process requirements of the host system (e.g. data bytes directly representing alphanumeric characters). Thus, the DSP acts as the equivalent of multiple different types of modems in performing required conversions.

Abstract: A special purpose circuit unit, responsive to a special BBD instruction, provides for more efficient execution of program branches required in poll and test type routines used by data processors. This unit can easily be added to almost any contemporary processing system to speed up performance of priority branch operations. It includes: a stack of registers loadable with branch addresses designating locations of branch target instructions, an input register for holding bits representing branch conditions accessible from immediate (programmable) storage, and a programmable priority encoder responsive to the BBD instruction to select an address from the stack in accordance with the position in the input register of a highest priority one of the bits representing an active request for instruction branching. The selected address is used to fetch an instruction representing the start of a program segment for attending to the selected branch condition.

Abstract: In a modem receiver having a fixed sample rate relative to incoming symbols and a tapped delay adaptive equalizer with fractional tap spacing, coefficients used in the equalization computations are rotated relative to a reference tap in order to compensate for relative drift between incoming signals, representing real (i.e. non-training) data, and the clock controlling sampling. By itself, such rotation would tend to distort received data by shifting the sampling phase away from the center of the received symbols. Logic means included herewith operates to prevent such distortion, so that the integrity of the data output of the receiver is unaffected by the rotation. In the disclosed embodiment, such logic means operates to shift the phase of the "sum of products" computation (product of data and tap coefficients) relative to the flow of data into the fractionally spaced delay network.

Abstract: A cathode ray tube display device has conductive plates mounted adjacent the four sides of the CRT faceplate. These plates are positioned to sense electromagnetic noise radiation generated by the CRT. The plates are coupled to differential circuits so that normally the noise signals generated in the plates cancel. However when a finger or other object is placed at or near the CRT faceplate, the noise radiation field is disturbed, and the changed signals generated in the plates are sensed by the circuits to provide output signals indicative of the coordinate position of the object at the faceplate. The plates are preferably mounted in the front bezel of the display cabinet.

Abstract: A computing system storage addressing apparatus which extends the addressing capability of an address bus to enable direct storage (memory) storage access (DMA) channels to operate simultaneously in the same or different storage page. The computing system includes a processor, a plurality of storage devices, a data bus and an address bus interconnecting the processor and the storage devices, a DMA device controlling connection of a plurality of DMA channels to the address bus and data bus, a plurality of address register means for storing page address signals loaded from the processor, and gating means for gating to the address bus page address signals from an address register means corresponding to a currently active DMA channel.

Abstract: In a communication system wherein stored data file record entities are designatable by common names unrelated to their storage locations in the system, names are adopted selectively as unique or non-unique. As a check on uniqueness, requests to entities bearing unique names require a response by each system station at which entities so named are stored. More than one response is treated as a system error. By present conventions, requests to entities with non-unique names do not require responses. Applications made possible by non-unique names of this type are described in the present disclosure.

Abstract: For facilitating data communication between entities in a local area network (storage files, programs, devices, human operators, etc.), a method is disclosed for addressing such communications to logical names adopted for the entities; rather than to discrete physical locations in the network. The subject method allows for extension of name-directed communications across bridges (between separate communication media or between discrete frequency channels on one medium). Extensions of such communications across bridges are conditioned on the handling of respective communications within the channel or medium leading to respective bridges. If a named entity is reachable within a channel or medium leading to a bridge, the communication will be acknowledged by the processing facility at the node serving that entity, and the communication will not be extended.

Abstract: A method and associated apparatus are disclosed for scanning documents and producing electronically stored signals corresponding to images on the documents. A stripe pattern of lines obliquely inclined relative to the direction of document movement provides precise indications of "pel" increments of document displacement relative to the image sensing apparatus. Using these indications, the system is effectively rendered insensitive to interruptions of document motion and/or variations in document motion speed. For example, this enables a system having limit buffer storage capacity to capture a full document image; by intermittently scanning portions of the image which fill the store, and halting document motion between scans of successive portions to allow for processing of the partial image data between the buffer store and other parts of the system's memory.

Abstract: Technique for dynamically maintaining alignment of servo controls in a disk drive system which uses external indicia to position the head assembly between tracks containing embedded servo signals; the latter used to control track following. Plural pairs of phase staggered track reference signals are derived from the external indicia, and during system initialization an optimal pair is selected for controlling head positioning. The system is initialized both at power up time and after detection of certain errors. The selection is made by using each pair separately to direct positioning of the head assembly over a predetermined range of sampling positions at each of which centering offsets relative to the embedded servo signals are measured and recorded in association with the respective pair. Based on an evaluation of these offsets, the system microprocessor selects a reference signal pair having the least average offset to control subsequent head positioning operations.

Abstract: In a local area network for data communications, stations which distributively control their access to a common bus or other medium are able to identify the location of any "hot" station transmitter (one stuck continuously in an "on" condition which cannot be isolated from the medium). Such networks are effectively disabled by a hot carrier, since each station conditions its access on sensing the medium as previously idle. The present "loop test" method permits all stations in the network to quickly establish the location of a hot transmitter, and thereby quickly direct field repair personnel to that location. It also permits operators to take action to physically disconnect the faulty transmitter from the medium, so that the other stations may continue to use the network until the fault is repaired.

Abstract: A refresh generator system for a dynamic memory in a data processing system, including a processor which is responsive to a hold request signal to relinquish control of the local bus and generate a hold acknowledge signal, comprises logic means to generate a hold request signal in response to an output from a refresh timer circuit. A logic circuit is responsive to a hold request, a corresponding hold acknowledge, and the timer signal to generate a refresh control signal. This signal generates a refresh signal for the memory control circuits, increments a counter circuit and initiates operation of a sequencer circuit. The sequencer then gates the output of the counter circuit to provide a memory row address and thereafter provides a memory read output to refresh the memory row defined by the address and lastly resets the circuit to terminate the hold request signal.

Abstract: In a CRT display device system, an upper assembly, including the display device, is tiltable on a supporting base assembly. A gear segment at each end of the upper assembly rests on a pair of pinions on the base assembly. The radius of curvature of each gear segment is centered on a horizontal line passing across the display device and through or near the center of gravity of the upper assembly. As the upper assembly is tilted, it pivots about this line and therefore remains substantially in balance for all angles of tilt. To provide static rest pressure to prevent unwanted tilting movement and also to minimize backlash, the pinions in each pair are coupled together through an idler pinion.

Abstract: A transformer assembly suitable for use in very high frequency (VHF) switching power supplies that maintains a low leakage inductance between critical transformer windings while complying with the physical and electrical requirements imposed by standards for primary to secondary isolation. The transformer includes a telescopic bobbin assembly with an inner and an outer section that telescope together to form an interior clearance space or chamber between the two sections. The interior chamber has a narrow conduit exiting to the exterior of the bobbin assembly. Described are two embodiments for a transformer used in a forward-averaging type converter and a third embodiment for a transformer used in a frequency modulated converter.

Abstract: In this data communication system, stations linked to a single line bus exchange information in a bit-serial asynchronous format in which transitions between stop and start signals mark beginnings of information bytes. The stations use a modified CSMA/CD protocol (carrier sense multiple access with collision detection) to obtain sending access to the bus. During information transfers, durations of stop signals are less than a predetermined limiting time length, but long enough to allow general purpose processing equipment at a station to participate directly in the real time process of information reception, thereby avoiding the need for having complex and costly adapting equipment interface between the bus and such processing equipment. When any transmission concludes, the bus remains at the stop signalling level. By conditioning detection of bus availability on timeouts conducted while the bus is in this condition, stations then ready to transmit avoid interfering with on-going transmissions.