Abstract: This I/O interface permits attachment of a data processing system to devices having different "handshaking" protocols and bit-parallel data exchange capacities. Handshaking control circuits permit the system to communicate with devices variously in pulsed and interlocked modes. Timer circuits provide a variety of different time reference signals for transfer to devices. Switching options associated with the timer permit selective use of timer outputs as pulsed mode handshaking functions. A counter circuit and associated interface port permit the system to count events associated with device-originated pulses. A switching option permits the counter incrementing operations to be governed by timer outputs. The interface also contains path selection lines. In one mode these lines define high speed exchange of data between a primary system processor and devices in various bit-parallel formats and over various buses designatable by a systems processor.

Abstract: A microcomputer system includes a main processor, a memory and a direct memory access controller (DMA) effective to control direct data transfer between the memory and input/output devices on channels. Bus control for data transfer is switchable between the DMA and processor by a hold request/acknowledge handshaking sequence between the DMA and processor. A control line from the channels is activated by a peripheral processing device on a channel when it wishes to gain control of the busses for data transfer. Logic means coact with the handshaking sequence to determine which device gains control of the busses. This logic is responsive to the DMA address enable output (AEN), the hold acknowledge output of the main processor (HLDA) and the channel control line output (-MASTER). When all these are deactivated, control passes to the main processor, when AEN and HLDA only are activated, control passes to the DMA controller and, when all three are activated, control passes to the peripheral processing device.

Abstract: Substitution of a general purpose data processing system for special purpose magnetic tape recording equipment, in certain existing network environments--one example being present telephone call billing networks--offers advantages in respect to equipment costs and data handling efficiency, but requires presently disclosed adaptation for effecting the substitution efficiently and with complete transparency to unaltered parts of the environmental (host) network. While simulating a data recording operation the substituted system receives an arbitrary length train of data bytes clocked at a first rate followed by a cyclic redundancy check (CRC) byte timed at a slower second rate. In order to maintain network transparency, the substituted system must retransmit the data and CRC check bytes, in their received order and at their respective reception rates, after a delay associated with the physical separation between recording and reproducing heads in the "native" tape recording equipment.

Abstract: This adapter contains two separately controllable sections, each transferring data in various formats between a peripheral device interface and either a microprocessor contained in an associated I/O controller or a host processor or both. Dedicated controls enable the adapter to operate autonomously after being prepared by the microprocessor. Separate but interconnectable handshaking controls enable the sections to operate either asynchronously or in time coordination with each other. Handshaking controls in plural adapters are interconnectable to coordinate related transfers of data between a device and one or more hosts via plural adapter paths. Programmable commands enable the microprocessor to condition the adapter to conduct various data transfers autonomously. Such data can be transferred to or from the device interface in various bit-parallel formats defined by the commands, and from or to the host processor, the microprocessor, or both the host processor and microprocessor concurrently.

Abstract: As a specific improvement to a previously known PLA (Programmed Logic Array) structure, formed by FET devices in serially chained charge transfer circuits, the presently disclosed "modified" PLA structure comprises a combination of: (a) level shifting circuitry, integrated into bit partitioning stages of the known structure, for reducing voltage swings in the outputs of those stages and thereby reducing spurious couplings to the following AND array stage as well as decreasing operational delays of the latter stage; (b) discrete capacitance, added at the output end of the OR array stage of the known structure, for sustaining and reinforcing charge conditions accumulated in that stage prior to readout (validation clocking) of that stage; and (c) a source of time related clocking functions coupled to stages of the modified structure, with the timing relationships selected so as to reduce operational delays of the entire structure while improving its integrity of operation.

Abstract: This secondary processing attachment to a primary (host) data processing system provides a dual mode I/O operation having unique "real time" applications. In this mode the attachment subsystem may exchange data concurrently with two potentially separate storage areas in host system main storage, under the direction of a single device control block (DCB) command descriptor prepared by host system software. Examples of real time processing applications include encryption and decryption of "secure" data by the attachment subsystem, matrix multiplication, or signal processing operations by the subsystem, and conservative movement of data between host storage and process control devices which link to the attachment subsystem via a device multiplexor and are co-addressed with that subsystem (by the host system).

Abstract: A method of initializing non-synchronous peer-to-peer data communication rings, and for effecting error recovery in such networks. On detection of error, each station operates in a purging configuration to clear the ring. In the purging configuration the station's receiving circuits are isolated and its transmitting circuits transmit "clear" signals containing this station's own address as destination. These signals serve to purge all potentially erroneous information in all upstream stations which then are operationally connected to that station. If a loss condition is persistent the station operates first in a "bypass" configuration for a third predetermined time interval, then in the purging configuration for the second time interval, and then resumes normal operation. In the bypass configuration the station's ring input is connected directly to its output and the (locally clocked) output of its transmitting circuits is connected to the input of its receiving circuits.

Abstract: A dual mode microprocessor acts either as a front-end IO controller processor relative to a primary host processor and device or as a secondary data processor having independent storage, processing and IO capabilities. Host software prepares a list of device control block (DCB) arrays, which contain primary commands interpretable by the microprocessor so as to evoke these modes. Each DCB contains a chaining bit permitting its interpretation sequence to be chained (or not chained) to another DCB sequence, and a mode bit defining either a high speed DI/DO (HS) mode of operation or a programmable offline (PO) mode. In HS mode the microprocessor conditions associated adapters to transfer a specified amount of data between the host memory and device, performing this transfer in an autonomous manner, i.e., without assistance from either processor.

Abstract: Groups of stations operate in TDMA mode relative to associated frequency-separated transponder segments of a satellite repeater. Stations at radio signaling modes in all groups key to a common frame timing reference. The TDMA frame is partitioned repetitively into IN GROUP and CROSS GROUP intervals, each susceptible of containing multiple demand assignable burst time slots. Each node may transmit TDMA bursts (of time compressed and time multiplexed information signals) in assigned slots in either interval (or both). Such bursts are carried only on the transponder radio frequency associated with the respective group. Station receivers are adaptive to switch local oscillator frequencies in synchronism with transitions between IN GROUP and CROSS GROUP periods, and thereby adaptive to receive signals from stations in both groups.

Abstract: Multiple stations exchange information without central supervision. Stations requiring a cycle of access time on a shared time-divided bus participate in a cyclic access resolution process. The station having highest priority for a next bus cycle indicates its precedence to the other stations, and assumes exclusive use of the bus in the next cycle. The bus may comprise separate sections for data and response communications. Separate access resolution processes are conducted relative to each section. After gaining access to the bus for one cycle of data transfer a station becomes ineligible to compete for access to the data section until it receives an associated response. Accordingly receiving stations may control both the rate of data transmittal and the rate of access competition activity at associated origin stations. The data and response communications may include address information for enabling stations to intercommunicate directly in pairs.

Abstract: In a microprogram controlled processor a master mask signal, generated selectively under microprogram control, synchronizes the handling of asynchronously generated interruption requests to desired sequence stages in the interpretation of program instructions. A programmed interrupt request (PIRR) associated with the interruption priority level of the program currently in control of the processor is maintained effective for a limited period of time after the associated program assumes control. This period is determined by the presence of a PIRR (-bit) which is interruptable by any higher priority level interrupt request. If a PIRR bit representing an interrupted program is still on when servicing of a higher priority level interrupt request is concluding control is returned to the interrupted program. In order to avoid possibly locking out programs which are not associated with asynchronously generated interrupt requests--e.g.

Abstract: In a micro-controlled data handling system the number of lines and pins required to transfer control signals from the microprogram controls to be integrated circuit modules controlled by such signals is conserved by using two bussing paths for distributing the control signals to the modules. A first path is dedicated exclusively to pre-decoded control signal functions and a second path is shared for transferring both data and control signal functions. Each controlled module contains an additional decoding circuit for combinationally decoding control signal functions received through both paths.

Abstract: Storage access requests are forwarded from plural input/output channels to shared main storage. An address word in each request designates the identity of the source channel (CHID) and "destination" address (of a doubleword space in storage relative to which one, two or four "data" words shall be transferred). EOT tag signal provides demarcation of requests and also uniquely identifies "1-wide" input (Store) requests. Quadword (QW) tag, presented with "4-wide" requests, enables the storage access system to use a single address in the request to locate two contiguous doubleword spaces in storage. Data tags (D1, D2), presented on a selective basis enable the access system to selectively steer (reorder the positions of) data words in an input request relative to word halves of the addressed space.

Abstract: A circuit for interfacing an AF line to a central unit makes use of an RF transformer Tr. Said transformer is so arranged that the source AF signal to be transmitted modulates an RF carrier generated in a primary winding of the transformer and the resulting modulated signal in the secondary winding is demodulated before being transmitted to a line which is thereby linked to the source.

Abstract: The Channel Bus Controller (CBC) transfers information between groups of input/output channels and processor storage. Storage receives or dispenses two data words per access operation. Interfaces for transfers from the channel groups to the CBC are advantageously one word wide; since each output (fetch) request consists of a single request word. Information sent by each group is assembled into three-word units (a request word and zero, one or two data words) in a respective channel bus assembly register (CBAR). The assembled unit is passed from the CBAR to a respective area of an In Buffer array and from that array to storage. Zero filler words are inserted into unused data word positions. A channel request may be tagged to designate a transfer of four data words. If the transfer is an input the four data words are sent to the CBC with a single request word.

Abstract: This adapter operates in time division multiplex mode between an input/output channel processing subsystem and a storage access subsystem of a data processing system. The adapter is capable of sustaining multiple processes of information transfer concurrently relative to both subsystems. It is also capable of concurrently sustaining ancillary processes for verifying and timing out individual transactions of the information transfer processes.

Abstract: A hierarchical memory for a data processing system which is comprised of a number of different independent storage modules and a main memory backing store. Each data handling element of the system has an independent storage module associated with it as a dedicated buffer. A larger high speed main storage is used as a backing store. Each data handling element presumes that any data it needs is located in its dedicated buffer. If the data is not in the dedicated buffer, the data handling element scans all the other buffers until the desired data is located.

Abstract: An improvement over an analog-to-digital converter in which a phase-locked loop (including a voltage controlled oscillator, a feedback path, and a phase discriminator) supplies clocking signals to a counter. The clocking signals are gated to the counter by a circuit which energizes a gate in response to a known reference signal and deenergizes an gate in response to the unknown source signal. The resultant count in a measure of the phase difference between the source and reference signals. Accuracy and stability derive from maintenance of a predetermined phase-locked relationship between a signal derived through frequency division of the loop output signal and the cyclic reference signal which is the reference for gating the counts to the counter. The loop output frequency is a harmonic of the frequency of the reference signal. Feedback phase control is developed through interaction of the frequency divided loop output signal with the reference signal in the phase discriminator circuit.

Abstract: A film for use in Lippmann photography is formed with a photosensitive emulsion on a transparent base and a separable reflective layer adhering to the emulsion. This separable layer may be a reflective coating carried by a soluble coating, or both soluble and insoluble coatings, or may be a reflective coating of a normally liquid metal which adheres to the emulsion and is readily separated by solvent or reactant.

Abstract: A method and associated apparatus for efficiently establishing a "self-sustaining" split in a rotating stack of floppy type storage disks in a form suitable for read/write transducing access. The formation of such splits is fully described in U.S. Pat. No. 3,936,800 to McGinnis et al. In the present method a partial split formed at one disk interface position is used as a stable reference for detecting the location of that interface position relative to a target address position. The form of the partial split is not suitable for storage transducing access. However, the partial split forms much more quickly than the self-sustaining split. If the deviation from the target position is zero the partial split is transformed directly into the self-sustaining fully accessible form by controlling internal ventilation pressure between the disks in accordance with said patent 3,936,880. If the deviation is not zero the mechanism forming the partial split (e.g.