Abstract: A monitor analyzes and generates a profile of an Internet website data transmission. The profile indicates the relative load and/or execution times of different components of the data, including text, images, and Java code. The profile is displayed and an end-user deselects one or more of the data components which are of marginal interest but contributing to the webpage load or execution times, whereupon the altered profile is stored. During a next access of the website, the altered profile is retrieved and utilized to selectively control a more limited load and/or execution of subsequently transmitted website data by eliminating the previously de-selected data types. The load or execution times associated with pages of the website are thereby reduced. In one embodiment, the profile is pre-generated and stored with the website data and transmitted in the website data transmission for display and alteration.

Abstract: In one form, apparatus for aligning clock signals includes first and second logic circuitry for receiving respective first and second clock signals. The first and second clock signals are substantially synchronized and operations of the first logic circuitry and second logic circuitry are clocked by the respective first and second clock signals. The first logic circuitry receives a third clock signal derived from the second clock signal, and by repeatedly sampling the third clock signal with the first clock signal, the first logic circuitry repeatedly detects relative phase relations of the first and third clock signals. The second logic circuitry adjusts the phase of the third clock signal responsive to an accumulation of the phase relation detecting.

Abstract: In one aspect, a method for performing clocked operations in a device includes performing, in a device, first and second operations responsive to a clock having a primary frequency f. The device is capable of performing the operations within X and Y cycles of the clock, respectively. X cycles of the clock correspond to a time interval T1 with the clock operating at the frequency f, and, accordingly, the device is capable of performing X/Y instances of the second operation within time interval T1 with the clock operating at the frequency f. During the time interval T1 at least one extra cycle of the clock is generated to reduce performance time for the first operation. An affect of the at least one extra cycle is masked with respect to the second operation, so that instances of the second operation during the interval T1 remain no greater in number than X/Y.

Abstract: A method of designing a system on a chip (SoC) to operate with varying latencies and frequencies. A layout of the chip is designed with specific placement of devices, including a bus controller, initiator, and target devices. The time for a signal to propagate from a source device to a destination device is determined relative to a default propagation time. A pipeline stage is then inserted into a bus path between said source device and destination device for each additional time the signal takes to propagate. Each device (i.e., initiators, targets, and bus controller) is designed with logic to control a protocol that functions with a variety of response latencies. With the additional logic, the devices do not need to be changed when pipeline stages are inserted in the various paths. Registers are utilized as the pipeline stages that are inserted within the paths.

Abstract: Disclosed is an apparatus and method for decreasing the timing delay variation of output signals obtained from an SOI technology sense amplifier. The cross-coupled latch includes FETs where the body is connected to one of source and drain to minimize switching history effects while the input FETs have a higher than normal gate switching voltage to increase input signal sensitivity.

Abstract: A method and system are described for efficiently overriding a value of a net in an array during execution of a test routine. The logic simulator machine is simulating a logic design which includes the array and multiple nets. A current value of the net is set equal to an override value. A normal update to the array is permitted to occur during execution of a single cycle of the test routine. A determination is then made regarding whether the override value is still stored in the array for the particular net. If the override value is not still stored in the array for this net, normal updates to the array are prohibited during a single cycle of the test routine. During this cycle of the test routine, the override value is then again stored in the net as the current value of the net. This override value is thus made available to be read during this cycle of the test routine while writes to the array are disabled.

Abstract: A method, system, and apparatus for maintaining the contents of a self-refreshable memory device during periods of data processing system reset is provided. In one embodiment, a refresh controller receives an indication that the data processing system is being reset. If necessary, the refresh controller modifies the signal from a memory controller to the memory device such that the memory device is placed in a self-refresh mode. The refresh controller keeps the memory device in the self-refresh mode until the data processing system re-enables external refresh signals.

Abstract: An improved cell circuit for data readout with reduced number of read wordlines is provided in a memory block of a multiport memory array. The number of read wordlines is significantly reduced by using a decoder between the read wordlines and a multiplexer in the cell circuit. The memory block has a plurality of address inputs and stores a plurality of write data signals. In the cell circuit, the decoder receives as decoder inputs a subset of the address inputs and outputs a plurality of select signals. The multiplexer is coupled to the decoder to receive the select signals and select one of the write data signals based on the select signals. Additionally, the read wordlines are coupled to the decoder for carrying the subset of the address inputs to the decoder.

Abstract: Several local clock buffers are disclosed, each including an input section and an output section. The input sections are substantially identical, and include control logic and gating logic. The control logic produces a gating signal dependent upon multiple control signals and a time-delayed global clock signal. The gating logic produces an intermediate clock signal dependent upon the global clock signal and the gating signal. The output section produces at least one local clock signal dependent upon the intermediate clock signal. In one embodiment, the output section produces a first local clock signal dependent upon the intermediate clock signal and a second local clock signal dependent upon the first local clock signal. In another embodiment, the gating logic produces the intermediate clock signal dependent upon the global clock and gating signals and a feedback signal. The output section produces the feedback signal and one or more local clock signals.

Abstract: The present invention provides a method and an apparatus for generating a phase error signal from a reference signal and a feedback signal using a modified reset generation mechanism. An input circuit receives a reference signal and a feedback signal. A phase error detector circuit generates a phase error signal based on the reference signal and feedback signal. The input circuit is reset and, after a delay, the phase error detector circuit is reset. The delay is selected so that there is no jitter associated with the dead zone.

Abstract: A bus architecture is provided to facilitate communication between independent bus masters and independent bus slaves by having two or more bus arbiters in a system-on-chip (SOC) system. Each bus master in the system is coupled to all bus arbiters in the system, so that each bus master can access a corresponding bus slave concurrently as well as sequentially. Such concurrent communication carries not only read and/or write data but also a target address of the corresponding bus slave, thereby enabling true concurrency in data communication between bus masters and bus slaves.

Abstract: In one aspect of the invention, a method for testing includes interposing a tester between first and second logic. The first logic and second logic have respective first and second output drivers. The tester operates in test cycles to detect dynamic contention responsive to a signal asserted by the first driver during one of the test cycles and a signal asserted by the second driver during an immediately succeeding one of the test cycles. Static contention is detected responsive to a signal asserted by the first driver during one of the test cycles and a signal asserted by the second driver during the same one of the test cycles.

Abstract: A system and method are provided for improving performance of a computer system by providing a direct data transfer between different processors. The system includes a first and second processor. The first processor is in need of data. The system also includes a directory in communication with the first processor. The directory receives a data request for the data and contains information as to where the data is stored. A cache is coupled to the second processor. An internal bus is coupled between the first processor and the cache to transfer the data from the cache to the first processor when the data is found to be stored in the cache.

Abstract: The invention includes a circuit for aligning the phase of a clock derived from a frequency multiplied version of a reference clock used in a computer system. The dynamic phase alignment circuit includes a few logic gates to perform the operation of delaying the derived clock, detecting its phase misalignment, and correcting such misalignment by incrementally aligning the phase of the derived clock to the reference clock. The invention is capable of aligning the phase of a derived clock to a reference clock in a computer system whose CPU operates at as high a frequency as about 500 MHz or higher.

Abstract: A method and an apparatus for suppressing errors reported by an error check function of a circuit. The method and apparatus utilizes a shifter to provide an enablement bit for the error reporting. An error is reported only if the enablement bit is set such that it allows the error to be latched through the circuit.

Abstract: Navigating a UAV including orbiting a waypoint including defining four bracket lines surrounding a waypoint, flying the UAV from a course segment having coordinate values in a range into a course segment not having coordinate values in the range, wherein a bounding bracket line defines a boundary between the segments; selecting, a heading parallel to a bracket line in dependence upon an orbital direction; the UAV in the orbital direction to fly on a the heading; and repeatedly: flying the UAV from a course segment having coordinate values in a range into a course segment not having coordinate values in the range, wherein a bounding bracket line defines a boundary between the segments; and turning the UAV in the orbital direction to fly on a heading parallel to the bounding bracket line.

Abstract: A non-integer fractional divider is disclosed. According to the present invention, the non-integer fractional divider comprises means for dividing a reference clock signal having a period ‘P’ by a non-integer ratio ‘K’. In a preferred embodiment, the divider comprises means for receiving a plurality ‘N’ of clock signals issued from the reference clock signal and wherein each clock signal is equally phase shifted by a ‘P/N’ delay one over the other. Selection means are coupled to the receiving means for selecting a first and a second clock signals between the plurality ‘N’ of clock signals. The selected clock signals are such that the phase shift delay between the two selected clock signals is representative of the non-integer value of the ratio ‘K’. The selected clock signals are combined into combining means to generate a clock signal being phase shifted by the non-integer part of the non-integer ratio.

Abstract: An apparatus and method for passing messages through a bus-to-bus bridge while maintaining ordering. The method comprises passing messages into a message container in the bus bridge without using the bridge buffer, setting a flag that tracks all the writes in the write queue ahead of when the message was put into the message container, blocking the receiving device on the bus connected to the bridge from accessing the message container until the flag is cleared, and clearing the flag when all the writes put into the write queue ahead of when the flag was set have been written to local memory on the receiving bus, then allowing the device on the receiving bus that is the intended recipient to receive the message.

Abstract: A method for rendering graphics on a server. In a preferred embodiment, a server receives a request from a requesting device for graphics. The server determines the fastest available rendering resource and dispatches the request to this fastest available rendering resource. Once the graphics have been rendered, the server sends the graphics to the requesting device for presentation to a user.

Abstract: For each predicted branch within a processor, an entry is maintained within a branch history table. The entry within the branch history table also includes an indication of the past record for that particular branch instruction, which indicates how correct the branch prediction has been in the past. When the field value associated with the predicted branch exceeds a certain threshold, indicating that the past predictions associated with that branch instruction have been at an unacceptable level, then the speculative branch instructions dispatching is suspended for that particular branch instruction. Alternative embodiments utilize a global indicator for suspending or cancelling instruction dispatch when the frequency of previous incorrect branch predictions increases beyond a preselected threshold.