Abstract: Data loaded from system memory to a cache within a multiprocessor system is set to the exclusive coherency state if no other cache or processor has a copy of that data. Subsequent accesses to the data by another processor or cache which are snooped by the data owner result in an exclusive intervention by the data owner. The data owner sources the data to and shares the data with the requesting device on a read and transfers exclusive ownership of the data to the requesting device on a read with intent to modify. Unmodified intervention with cache-to-cache transfers over possibly much slower accesses to memory is thus supported by the multiprocessor system without requiring additional tag or status bits in the cache directories, saving a significant area.

Abstract: A processor capable of executing vector instructions includes at least an instruction sequencing unit and a vector processing unit that receives vector instructions to be executed from the instruction sequencing unit. The vector processing unit includes a plurality of multiply structures, each containing only a single multiply array, that each correspond to at least one element of a vector input operand. Utilizing the single multiply array, each of the plurality of multiply structures is capable of performing a multiplication operation on one element of a vector input operand and is also capable of performing a multiplication operation on multiple elements of a vector input operand concurrently. In an embodiment in which the maximum length of an element of a vector input operand is N bits, each of the plurality of multiply arrays can handle both N by N bit integer multiplication and M by M bit integer multiplication, where N is a non-unitary integer multiple of M.

Abstract: An apparatus and method for performing partial logical shifts of a multiple-word logical signal is implemented. Portions of an input logical signal to be shifted are input to a plurality of barrel shifters. Each barrel shifter performs a rotation of its associated input portion. Each corresponding rotated portion output therefrom is masked with a preselected mask having m trailing zero bits, for a left shift, or m leading zero bits, for a right shift. Rotated portions from barrel shifters succeeding, for a left shift, or preceding, for a right shift, the barrel shifter associated with the corresponding rotated portion are masked with a complementary mask and logically combined with the masked rotated portion from the corresponding barrel shifter to form a corresponding portion of the shifted output signal.

Abstract: An out-of-order issue mechanism for a data processing system allows two out-of-order instructions to be issued to independent “pipes” from a window of four instructions currently queued for execution. If the two pipes execute floating pipe operations, dependencies between a computationally intensive floating point unit instruction (referred to as an fpu rr instruction) and the two previous computational intensive instructions having a target and a floating point register (the “fpr target”) are tracked to provide a mechanism that quickly determines when dependent data is available from one of the floating point unit pipes. The data is then used to preempt the issue of a dependent instruction until data is available. Additionally, this out-of-order issue mechanism recognizes when consecutive instructions are dependent upon a same operand.

Abstract: A computer modulates among a number of states. Information stored in the computer memory includes predefined categories of an expected external stimulus. For example, the stimulus may include events and the categories include types of events. Also stored in memory are the predetermined states and likelihood functions for transitioning from one state to another. The states may represent emotional states, and the events represent emotion bearing events. Each type of event may have predefined emotional characteristics, with the likelihood functions being response to the occurrence of the events, the categorization of the events, and the characterization of the event's category.

Abstract: A computer chassis for covering and protecting the components of a data processing system. In a preferred embodiment, the computer chassis includes a chassis bezel. The chassis bezel has a slotted opening there through for allowing a user to access a user changeable component in the data processing system. The chassis bezel is configured to accept a cover plate that will cover the slotted opening thus preventing access to the user changeable component.

Abstract: The present invention provides a method and apparatus for optimizing bus utilization while maintaining read and write coherence. More specifically the invention provides bus utilization optimization by prioritizing read transactions before write transactions, where there is no collision pending. When a collision pending is determined, then the read and write transactions are processed according to the age of the transaction(s) allowing for data coherency.

Abstract: A noise suppression circuit for suppressing noises above and below reference voltages is provided. The noise suppression circuit for suppressing noises includes a clamping transistor, a feedback circuit, and a presetting means for presetting an internal latch of the noise suppression circuit to a predetermined state. The predetermined state is a high state or a low state depending upon the type of noise suppression accomplished by the circuit. After the occurrence of a noise coupling event, the clamping transistor restores the state of a data input of a circuit to which the suppression circuit is providing protection. The feedback circuit then turns off the clamping transistor after a predetermined amount of time.

Abstract: A repeater circuit (10) includes a decoder arrangement (34) and an encoder arrangement (33). The decoder arrangement (34) is connected to an input transmission line to receive an input encoded signal comprising a signal at one of four encoded voltage levels. Each of the four possible encoded voltage levels represents a different combination of first and second digital data signals. The decoder arrangement (34) decodes the input encoded signal to produce the first and second data signals. These first and second data signals then serve as inputs to the encoder (33) which encodes the signals into an output encoded signal. The output encoded signal comprises a signal similar to the input encoded signal but restored to account for parasitic resistance associated with the input transmission line (21).

Abstract: In a voice actuated computer system voice command from an end user relevant to or promoted from a discrete location on a display screen are analyzed by the system. In response, a confirmation area is displayed on the screen at a location functionally related to the analyzed contents and context of the voice input or the screen location the utterance was prompted from. Within the confirmation area the computer interpretation of the utterance is displayed persisting and dissolving at selectively adjustable rates and times. Display of the recognized utterance is thereby placed in a confirmation area at variable locations where the user's focus is likely to be. Distractions are avoided associated with a fixed location confirmation area which obscures other content on the display screen and/or destroys end-user focus by requiring the eyes to shift from a location of current interest on the display screen to a different location wherein the confirmation is displayed.

Abstract: A method and system for deconfiguring a CPU in a processing system is disclosed. In one aspect, a processing system is disclosed that comprises a central processing unit (CPU), and a memory coupled to the CPU. The error status register for capturing information concerning the status of the CPU. The processing system includes a service processor for gathering and analyzing status information from the CPU error register. The processing system also includes a nonvolatile device coupled to the service processor. The nonvolatile device includes a deconfiguration area. The deconfiguration area stores information concerning the status of the CPU from the service processor. The deconfiguration area also provides information for deconfiguring a CPU during a boot time of the processing system. Accordingly, through the present invention, CPU errors are detected during normal computer operations by error detection logic.

Abstract: A method and apparatus is provided for implementing a cache control system effective to eliminate many of the timing problems occurring in dynamic, high bandwidth cache control systems. In one exemplary embodiment, a dummy content addressable memory (CAM) cell is provided and is strategically placed on the chip layout farthest away from the cache word line driver circuit. The dummy output signal is a required input to a cache hit evaluation circuit such that premature cache hit outputs are eliminated. The dummy cell is designed to quickly discharge a cache match line and indicate a non-hit status when any address bit line produces a mismatch indication, especially for expanded bandwidth and dynamic systems where the address lines are more extensive and the system is synchronized to predetermined clock cycles. The cache system further operates in a prefetch mode to determine hits for next in-line requested addresses.

Abstract: A key assembly includes a cover disposed over a transducer which is connected to a key acutator/interface disposed between the key transducer and a CPU. A tactile signal generator generates control signals from the CPU to activate the actuator/interface. The actuator/interface provides a signal appropriate to the particular transducer causing it to produce tactile feedback response to the key cover and user's touch. The key assembly may include a larger key cover disposed over a plurality of key transducers whereby the CPU causes texture and fine detail sensations variable over the key cover area by selective, variable actuation of the transducers. The end-user may thereby sense by physical contact with the large key cover electronically generated sensations of irregular surfaces or textures. Tactile profiles either user-specified or automatically invoked by a corresponding application vary the keyboard touch and feel as defined by the selected profile.

Abstract: For transmitting information on a plurality of integrated circuit conductive lines, n conductive lines are provided on a path in an integrated circuit. The path has first and second portions, and an interposing, transition portion. The lines have first positions with respect to one another in the first portion, and certain of the lines change relative positions in the transition portion, so that the lines have second positions with respect to one another in the second portion. The information is encoded in a format wherein no more than one of the n lines has a signal asserted thereon at a time, so that there is a reduction in noise induced among the lines.

Abstract: An interleaved data cache array which is divided into two subarrays is provided for utilization within a data processing system. Each subarray includes a plurality of cache lines wherein each cache line includes a selected block of data, a parity field, a content addressable field containing a portion of an effective address (ECAM) for the selected block of data, a second content addressable field contains a real address (RCAM) for the selected block of data and a data status field. Separate effective address ports (EA) and a real address port (RA) permit parallel access to the cache without conflict in separate subarrays and a subarray arbitration logic circuit is provided for attempted simultaneous access of a single subarray by both the effective address port (EA) and the real address port (RA). A normal word line is provided and activated by either the effective address port or the real address port through the subarray arbitration.

Abstract: A get request employing TCPIP sockets is issued which obtains requested HTML pages associated with the application from the web server. A search is executed extracting all links on the page automatically. The links are optionally sorted as designated in an input file or command line in random order so as to generate a typical access paths through the web server application during testing and verification thereof. The retrieved and extracted data is formatted and output in a common format employable in an input file by multiple test application tools which request, capture, store, verify data returned from, and stress the web servers and associated applications. In a preferred embodiment, server port, and server name specified by host name or address, may be designated either in the input file or command line.

Abstract: A computerized subsystem starts multiple user-defined threads, each of which is a virtual browser for a web site server application under test and executing on a web server. Each individual virtual browser requests and posts data to the server and corresponding server application under test at a rapid rate. Actual returned data is not saved but time of transaction and whether page is found and returned is logged. The server and port to test are user-specified in an input data file or can alternatively, by command line option. A repeat option causes the subsystem to loop through the input file a specified number of times, hours, and an indefinite repeat. User-specified sleep values slow down requests to simulate actual users. A wait option creates a semaphore causing all threads to wait for the semaphore which appear only after all threads are created, whereupon such threads begin execution simultaneously to maximize stress on the server and application.

Abstract: A system and method for automatically adjusting priority assigned to execution of applications, tasks, or workspaces. A display of visual indicators is provided, corresponding to a differing task. By selecting an indicator, priority given to task execution is altered as the task is moved into a focused state as a result of such selection. A window manager between a server and application registers in the server adjusted state of a particular application as either in focus or cleared. An application, through its corresponding window-id, detects from the server that an adjustment in priority is desired. A mapping function such as a lookup table maps the window id to a corresponding process-id which is then utilized by the application in a process table. The information from the window manager passed through the display server is utilized by the application to adjust its own priority relative to the remaining applications in the operating system's process table. A WM.sub.

Abstract: A method and system for autoconfiguring redundant arrays of memory storage devices contained within receptacles having one or more slots containing hardware sufficient to accept and electrically communicate with such memory storage devices. The capacities of the memory storage device receptacles for accepting memory storage devices are determined, and used to define an initial positioning of devices in at least one memory storage device receptacle. One or more asymmetrical groupings of memory storage devices is defined to permit an equation of electrically detected relative positions of the memory storage devices with actual physical positions within the receptacle. Thereafter, additional devices are added into the receptacles such that the ability to equate electrically detected relative positions of the devices with physical positions is preserved.

Abstract: A system resource monitor is provided to capture a data processing system's internal resource utilization, such as memory, CPU, or peripheral device availability/utilization. The captured `state` of the data processing system's resources is maintained in real-time, while the impact on the system's performance in providing such information is kept to a minimum. This is accomplished through a combination of various techniques, including specialized device drivers for the respective devices coupled with a unique data reduction technique. Such techniques include filtering only events which are of interest and combining similarly related events to reduce data processing requirements. This real-time support provides an immediate and accurate representation of the internal operations of the data processing system. Further, these resources can monitored at the process level of a multiprocessing system.