Abstract: A method and apparatus in a data processing system for generating a two dimensional display of a three dimensional object. Data is received representing the three dimensional object. Back-face culling is performed using a data structure, wherein the data structure includes a set of predetermined visibility data derived from the results of dot products of normal vectors with eye vectors. The two dimensional display of the three dimensional object is generated using results of the back-face culling.

Abstract: The phase of a memory clock signal is adjusted by advancing and/or delaying the phase. A configuration register is used to determine the phase adjustment of the memory clock signal. The value of the configuration register can be changed through software. This flexible phase adjustment technique is valuable in meeting various timing requirements in a source synchronous memory controller.

Abstract: A method for verifying a source-synchronous communication interface of a processor is disclosed. A software model of a first device having a source-synchronous communication interface and a software model of a second device capable of communicating with the first device via the source-synchronous communication interface are provided. The source-synchronous communication interface includes an applied clock line, an address line, an echo clock line, and a data line. A simulation of a data request from the first device model to the second device model via an applied clock signal along with an address on the applied clock line and the address line is initially performed. The requested data is then received by the first device model from the second device model via the data line after various delays between the applied clock signal and an echo clock signal on the applied clock line and the echo clock line, respectively. Finally, the requested data received by the first device model is verified as to its veracity.

Abstract: Data stream touch instructions are software-directed asynchronous prefetch instructions that can improve the performance of a system. Ideally, such instructions are used in perfect synchronization with the actual memory fetches that are trying to speed up. In practical situations, it is difficult to predict ahead of time all side effects of these instructions and memory access latency/throughput during execution of any large program. Incorrect usage of such instructions can cause degraded performance of the system. Thus, it is advantageous to measure the performance of such instructions.

Abstract: An apparatus for saturation detection and a method therefor are implemented. Selection circuitry selects a data value signal for outputting between an output from an adder receiving a pair of input operands, and a plurality of saturation value signals. Each input operand may include a plurality of subvector operands of a preselected data type, each data type has having a corresponding length. The selection circuitry selects the data value signal in response to a plurality of second signals. The second signals are generated from carry-out signals from the subvector operands, and first signals that are generated using instruction information for the executing instruction. The second signals may be generated by logically combining the first signals with carry propagate, carry generate and carry-out signals from carry lookahead logic receiving the subvector operands as input.

Abstract: A method for determining an equivalent load at the output of a gate driving an interconnect having resistive, inductive and capacitive elements. The method includes modeling the interconnect utilizing a passive driving point model to derive a realizable reduced order circuit for the interconnect. In an advantageous embodiment, the realizable reduced order circuit includes a first resistance parallel-coupled to an inductance and series-coupled to a pi-model equivalent circuit that includes a second resistance and first and second capacitances.

Abstract: A flexible, software configurable DDR read data path structure provides independently programmable sample stage and sample cycle capability. It also provides the capability to independently delay a read sample stage clock to support a wider range of data and data strobe (DQS) arrival times over a broad frequency range and subsequent sample stages to compensate for any resultant read cycle compression within any source synchronous interface. An SDRAM timing register is used to control read data path structure by changing bits in the register.

Abstract: An apparatus for compare and maximum/minimum and a method therefor are implemented. Selection circuitry selects a data value signal for outputting between an a pair of vector operands and “true” and “false” comparison value signals for the corresponding operand data type. Each input operand may include a plurality of subvector operands of a preselected data type, each data type has having a corresponding length. The selection circuitry selects the data value signal in response to a plurality of second signals. The second signals are generated from carry-out signals from the subvector operands, and first signals that are generated using instruction information for the executing instruction. The second signals may be generated by logically combining the first signals with carry propagate, carry generate and carry-out signals from carry lookahead logic receiving the subvector operands as input.

Abstract: A method for timing and noise analysis in designing data processing chips is provided. The process begins by wiring all unconnected nets in the design and then using a 2½ D capacitance extraction technique built into a detailed router to extract all of the wired nets. The data from the extracted nets is then process using a timing and analysis tool. Optimization programs are then used to generate fixes for any nets in the design which contribute to timing and noise failures. The present invention gives designers the capability of fast and accurate interconnect extraction within the routing tool. In addition, this technique is incremental. Any wiring changes can be quickly re-extracted, since only local information is required for extraction. This incremental capability allows designers to perform quick iterations of wiring, extraction and timing analysis.

Abstract: A method of arbitrating between cache access circuits (i.e., load/store units) by stalling a first cache access circuit in response to detection of a conflict between a first cache address and a second cache address. The stalling is performed in response to a comparison of one or more subarray selection bits in each of the first and second cache addresses, and further preferably includes a common contention logic unit for both the first and second cache access circuits. The first cache address is retained within the first cache access circuit so that the first cache access circuit does not need to re-generate the first cache address. If the same word (or doubleword) is being accessed by multiple load operations, this condition is not considered contention and both operations are allowed to proceed, even though they are in the same subarray of the interleaved cache.

Abstract: A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. Due to pin limitations that may be caused by large buses, functionality for address paths and data paths are implemented in the node controller and are implemented in physically separate components. Commands are sent from the node address controller to the node data controller to control the flow of data through a node.

Abstract: A single common symmetrical DDR read data path structure and corresponding storage addressing scheme is provided for implementing both N-bit and (N/2)-bit interfaces to a DDR memory. The read data path structure of the present invention uses a feedback loop of a lower data path to a higher data path in conjunction with the translation of the physical addressing of the data stored into a memory. The feedback loop and address translation mechanism is enabled for (N/2)-bit mode and disabled for N-bit mode. Normally, a multiplexer controlled by a static control is used to change the bit mode.

Abstract: Precharge circuitry for reading a data bit from a memory having at least two local bit lines comprises at least two precharge transistors for precharging the at least two local bit lines, at least two “keeper” transistors for keeping the at least two local bit lines, and a NAND gate for receiving the data bit from the memory via one of the at least two local bit lines and switching the at least two “keeper” transistors. The precharge circuitry does not need an additional inverter for switching any of the “keeper” transistors, thereby eliminating additional capacitance associated with the inverter and reducing unnecessary power consumption associated with the “keeper” transistors. Preferably, the transistors used in the precharge circuitry are p-channel metal-oxide-semiconductor field effect transistors (MOSFETs).

Abstract: A processor and method of fetching data within a data processing system are disclosed. According to the method, a first difference between a first load address and a second load address is calculated. In addition, a determination is made whether a second difference between a third load address and the second load address is equal to the first difference. In response to a determination that the first difference and the second difference are equal, a fourth load address, which is generated by adding the third address and the second difference, is transmitted to the memory as a memory fetch address. In an embodiment of the data processing system including a processor having an associated cache, the fourth load address is transmitted to the memory only if the fourth load address is not resident in the cache or the target of an outstanding memory fetch request.

Abstract: A circuit generating memory clock with phase advance and delay capability is provided. The phase of the memory clock is controlled by adjusting the configuration register bits. The circuit allows for a high degree of control and flexibility in the memory clock generation in that the memory clock relationship with respect to the memory command and data can be adjusted independently, thereby creating the ability to effectively adjust the memory interface timings such as setup time, hold time, and memory read data access time. Specifically, 0, 90, and 180 degree phase advance ability is combined with the ability to add delay in fine increments to achieve a more granular degree of phase adjustment.

Abstract: The present invention provides a method and apparatus for allowing autonomous, way specific tag updates. More specifically, the invention provides way specific tag and status updates while concurrently allowing reads of the ways not currently being updated. If a read hit is determined, then the read is processed in a typical fashion. However, if the read is a read miss and one of the ways is flagged as being updated, then all ways are read again once the specific way has completed its updated.

Abstract: A method for performing circuit analysis on an integrated-circuit design having design data available in different forms is disclosed. In accordance with the method and system of the present invention, the integrated-circuit design includes multiple networks, and the different forms of design data may appear within one of the networks. For all of the networks within the integrated-circuit design, different forms of design data are categorized into at least three databases. The first of the at least three databases may contain three-dimensional extraction information, the second of the databases may contain wiring information, and the third of the databases may contain pre-wiring information. For each of the networks, a determination is made as to whether or not three-dimensional extraction information is available. In response to a determination that three-dimensional extraction information is available, performing circuit analysis by utilizing the three-dimensional extraction information.

Abstract: An apparatus and method for determining power consumption in logic devices including mixed static and dynamic logic blocks is implemented. Input logical signals are tagged as having dynamical behavior or static behavior, and the power consumption of the logic block determined according to the behavior of the input signal. If an input signal has dynamic behavior, an output signal making a transition in response thereto will make two transitions per clock cycle, and the per cycle power consumption of the logic block is accordingly weighted. In another embodiment, a Boolean behavior signal is calculated for each block from clock phase tags and “one cycle per cycle” circuit level simulations. The per cycle power consumption of each logic block receives a weight in response to the Boolean behavior signal, according the behavior of the block characterized thereby.

Abstract: Network input processing is distributed to multiple CPUs on multiprocessor systems to improve network throughput and take advantage of MP scalability. Packets received on the network are distributed to N high priority threads, wherein N is the number of CPUs on the system. N queues are provided to which the incoming packets are distributed. When one of the queues is started, one of the threads is scheduled to process packets on this queue at any one of the CPUs that is availableat the time. When all of the packets on the queue are processed, the thread becomes dormant. Packets are distributed to one of the N queues by using a hashing function based on the source MAC address, source IP address, or the packet's source and destination TCP port number, or all or a combination of the foregoing. The hashing mechanism ensures that the sequence of packets within a given communication session will be preserved. Distribution is effected by the device drivers of the system.

Abstract: A crossbar is implemented within multimedia facilities of a processor to perform vector permute operations, in which the bytes of a source operand are reordered in the target output. The crossbar is then reused for other instructions requiring multiplexing or shifting operations, particularly those in which the size of additional multiplexers or the size and delay of a barrel shifter is significant. A wide shift operation, for example, may be performed with one cycle latency by the crossbar and one additional layer of multiplexers or a small barrel shifter. The crossbar facility thus gets reused with improved performance of the instructions now sharing the crossbar and a reduction in the total area required by a multimedia facility within a processor.