Patents Represented by Attorney Robert Ochis
  • Patent number: 5351001
    Abstract: A test fixture for testing microwave components enables components to be tested with high correlation between the component's test results and its operation in a system. The test fixture provides for non-destructive mounting of and connection of the component to the test fixture in the same manner as it will be connected in the final system and also provides for tailoring of the test connections as may be desired.
    Type: Grant
    Filed: April 5, 1990
    Date of Patent: September 27, 1994
    Assignee: General Electric Company
    Inventors: William P. Kornrumpf, David A. Bates
  • Patent number: 5345205
    Abstract: A multimodule microwave system is assembled in a physically compact, high reliability manner employing a high density interconnect structure to interconnect the different modules of a microwave system by rendering the portion of the interconnect structure between modules flexible and by folding the interconnect structure on appropriate sized mandrels between the modules to place the modules in a multi-tier physical stack. Shielding and hermetic packaging may also be provided.
    Type: Grant
    Filed: April 5, 1990
    Date of Patent: September 6, 1994
    Assignee: General Electric Company
    Inventor: William P. Kornrumpf
  • Patent number: 5082795
    Abstract: A self aligned method of fabricating a vertical channel insulated gate semiconductor device comprises providing a first layer of one type conductivity atop a partially processed wafer. A first protective layer is disposed over the first layer and a window is opened therethrough. A first region can be established through the first window and in the first layer. A trench is established through the first window, and extending entirely through the first region and first layer, into the partially processed wafer. An insulated gate is established in the trench to control the drift region electric field under reverse bias operation.
    Type: Grant
    Filed: November 1, 1988
    Date of Patent: January 21, 1992
    Assignee: General Electric Company
    Inventor: Victor A. K. Temple
  • Patent number: 5013696
    Abstract: Polycrystalline ceramic bodies having uniform transparent optical characteristics are produced by providing a green compact, presintering that compact at a temperature in the range from about 1,350.degree. C. to about 1,650.degree. C. until the closed porosity stage is reached, hot isostatic pressing the presintered compact to collapse substantially all pores disposed at grain boundaries and resintering the hot isostatically pressed compact at a temperature in the range from 1,700.degree. C.-1,950.degree. C. to cause grain growth under conditions in which pores, within those grains which are consumed by the growth of other grains, collapse as the grain boundary of the growing grain passes through the location of the pore in the smaller grain being consumed.
    Type: Grant
    Filed: September 25, 1989
    Date of Patent: May 7, 1991
    Assignee: General Electric Company
    Inventors: Charles D. Greskovich, William P. Minnear, Milivoj K. Brun, Robert J. Riedner
  • Patent number: 4992390
    Abstract: Improved trench gate field effect devices are provided by forming a thick oxide at the bottom of the trench. This thick oxide may be preferably formed by ion implantation into the bottom of the trench.
    Type: Grant
    Filed: July 6, 1989
    Date of Patent: February 12, 1991
    Assignee: General Electric Company
    Inventor: Hsueh-Rong Chang
  • Patent number: 4988412
    Abstract: Selective electrolytic deposition is provided on a body having a conductive surface comprised of two different conductive materials in which one of the conductive materials forms a surface layer upon exposure to a particular ambient environment and wherein that surface layer prevents electroplating on that material in the particular electroplating environment utilized for the electroplating of the desired pattern on the other conductive material.
    Type: Grant
    Filed: December 27, 1988
    Date of Patent: January 29, 1991
    Assignee: General Electric Company
    Inventors: Yung S. Liu, Herbert S. Cole, Renato Guida, James W. Rose
  • Patent number: 4982258
    Abstract: In a depletion mode thyristor of the type including a regenerative portion and a non-regenerative portion, the turn-off time for the thyristor is substantially reduced without producing a corresponding increase in the on-resistance of the device by providing a region of relatively low carrier lifetime in the non-regenerative portion of the device in the layer or layers in which charge storage limits the turn-off time for the device. Turn-off of the thyristor is accomplished by pinching off the regenerative portion, thereby diverting current into the low carrier lifetime non-regenerative portion.
    Type: Grant
    Filed: May 2, 1988
    Date of Patent: January 1, 1991
    Assignee: General Electric Company
    Inventor: Bantval J. Baliga
  • Patent number: 4969028
    Abstract: A high power semiconductor rectifier is constructed so that the rectifier is normally off and can be switched on by applying a bias signal to a gate of a metal-insulator-semiconductor structure monolithically integrated with the rectifier in such a manner as to induce a conducting channel between the anode and cathode of the rectifier. The device has both forward and reverse blocking capability and a low forward voltage drop when in the conducting state. The device has a very high turn-off gain and both high dV/dt and di/dt capabilities.
    Type: Grant
    Filed: March 8, 1990
    Date of Patent: November 6, 1990
    Assignee: General Electric Company
    Inventor: Bantval J. Baliga
  • Patent number: 4963951
    Abstract: The present invention relates generally to insulated gate transistors and more particularly, to laterally implemented insulated gate transistors having improved current capacity and improved immunity to latch-up. Specifically, it has been found that a lateral insulated gate transistor fabricated on a heavily doped substrate such as a p+ substrate exhibits improved current density. Further, the inclusion of an additional heavily doped region such as a P+ region proximate the base region contributes to improved latch-up immunity within the device.
    Type: Grant
    Filed: November 29, 1985
    Date of Patent: October 16, 1990
    Assignee: General Electric Company
    Inventors: Michael S. Adler, Deva N. Pattanayak
  • Patent number: 4963950
    Abstract: A depletion mode thyristor includes a plurality of regenerative segments and a plurality of non-regenerative segments, each of which is elongated in a first direction. Regenerative and non-regenerative segments are interleaved in a second direction perpendicular to said first direction. A plurality of regenerative segments may be disposed between adjacent non-regenerative segments. Adjacent regenerative or non-regenerative segments are spaced apart by gate electrode segments which are effective, upon application of an appropriate bias voltage, for pinching off the regenerative segments to force the current therein to transfer to the non-regenerative segments to turn the device off. This structure enables large quantities of current to be transferred from regenerative segments to non-regenerative segments during turn-off without inducing detrimental current crowding.
    Type: Grant
    Filed: May 2, 1988
    Date of Patent: October 16, 1990
    Assignee: General Electric Company
    Inventors: Hsueh-Rong Chang, Bantval J. Baliga
  • Patent number: 4961100
    Abstract: An insulated field effect semiconductor device having source and drain regions extending to opposed surfaces of its semiconductor body is bidirectional and capable of blocking voltages in either of two opposing polarities and comprises a four terminal device having source and drain electrodes disposed on the opposed surfaces and a base electrode all ohmically connected to corresponding portions of the semiconductor body. An insulated gate is provided in a trench which extends into the semiconductor body for controlling the conductivity of a channel region extending within the base region between the source and drain regions. The device is free of source-to-base and drain-to-base short circuits. Control circuits enable this device to conduct or block both polarities of a high current AC voltage applied across its source and drain terminals while preventing undesired avalanche breakdown within the device.
    Type: Grant
    Filed: June 20, 1988
    Date of Patent: October 2, 1990
    Assignee: General Electric Company
    Inventors: Bantval J. Baliga, Hsueh-Rong Chang, Edward K. Howell
  • Patent number: 4960613
    Abstract: The uniformity of a catalyst layer produced by laser decomposition of a catalyst source compound is substantially improved for patterned substrates whose characteristics vary along the path of a conductor line by providing a buffer layer of a metal such as Ti, Cr or Ni over the substrate prior to the laser induced decomposition of the catalyst source compound.
    Type: Grant
    Filed: October 4, 1988
    Date of Patent: October 2, 1990
    Assignee: General Electric Company
    Inventors: Herbert S. Cole, Yung S. Liu
  • Patent number: 4958211
    Abstract: An MOS controlled thyristor (MCT) provides insulated gate control of turn-off from the regenerative state for arbitrarily large currents. An emitter region of the thyristor is provided with a high injection efficiency portion which is resistively connected to an ohmic contact to the main power electrode for that emitter region. The turn-off gate controls a channel region through that emitter region which connects a source region to the adjacent base region. During gate induced turn-off, the resistive connection of the high efficiency emitter region to the power electrode provides an additional voltage drop over that of a forward biased junction to encourage the flow of carriers through the channel region into the source region to bypass the emitting junction.
    Type: Grant
    Filed: September 1, 1988
    Date of Patent: September 18, 1990
    Assignee: General Electric Company
    Inventor: Victor A. Temple
  • Patent number: 4942445
    Abstract: A lateral depletion mode thyristor has both of its power electrodes and both of its emitter regions extending to the same surface of the semiconductor wafer. The device operates with both a regenerative current path and a non-regenerative current path. An insulated gate electrode structure is disposed in a trench and configured to pinch off the regenerative current path to force the current flowing therein to transfer to the non-regenerative current path, thereby interrupting the regenerative action within the device and causing it to turn off. In some embodiments, a second insulated gate electrode controls device turn-on.
    Type: Grant
    Filed: July 5, 1988
    Date of Patent: July 17, 1990
    Assignee: General Electric Company
    Inventors: Bantval J. Baliga, Hsueh-Rong Chang
  • Patent number: 4942440
    Abstract: A high voltage P-N diode includes a P.sup.- substrate with a thin N.sup.- epitaxial layer thereon. An N.sup.+ cathode region extends into the N.sup.- epitaxial layer from the upper surface thereof. A P.sup.+ anode region extends into the N.sup.- epitaxial layer from its upper surface and surrounds the N.sup.+ cathode region. An N.sup.+ buried layer is situated between the P.sup.- substrate and the N.sup.- epitaxial layer, beneath the P.sup.+ anode region, and surrounds the N.sup.+ cathode region, as viewed from above. A further P.sup.+ region extends into the N.sup.- epitaxial layer from its upper surface and surrounds the N.sup.+ cathode region, and, in turn, is surrounded by the P.sup.+ anode region. In an exemplary embodiment, a MOSFET is included to alternately connect the further P.sup.+ region to the P.sup.- substrate and to open circuit the further P.sup.+ region. With the further P.sup. + region open circuited, the P-N diode has a low on-resistance when it operates in its current-conducting state.
    Type: Grant
    Filed: September 9, 1988
    Date of Patent: July 17, 1990
    Assignee: General Electric Company
    Inventors: Bantval J. Baliga, Eric J. Wildi
  • Patent number: 4941026
    Abstract: An improved conductivity vertical channel semiconductor device includes an insulated gate electrode disposed adjacent a substantial portion of the voltage supporting region. In response to an appropriate bias, the control electrode couples to the electric field originating on charges within the voltage supporting region to reorient the electric field associated with those charges toward the gate electrode and transverse to the direction of current flow through the device. Improved control of the electric field within the voltage supporting region allows the doping concentration, and hence the conductivity of the channel, to be improved without a concomitant decrease in breakdown voltage. Accordingly, the channel width and cell repeat distance of the improved device can be reduced, allowing for an improved current density to be established throughout an overall device cell structure. The charge control region of the voltage supporting layer exhibits an aspect ratio of 0.5.
    Type: Grant
    Filed: August 26, 1988
    Date of Patent: July 10, 1990
    Assignee: General Electric Company
    Inventor: Victor A. K. Temple
  • Patent number: 4939101
    Abstract: Wafers which are direct bonded to each other in accordance with prior art processes suffer from voids at their bonded interface. Annealing such composite structures at high temperature and high pressure (for silicon wafers preferably about 1,100.degree. C. and 15,000 psi) eliminates all voids which are not a result of the presence of a particle on one of the wafers at the time of mating.
    Type: Grant
    Filed: September 6, 1988
    Date of Patent: July 3, 1990
    Assignee: General Electric Company
    Inventors: Robert D. Black, Stephen D. Arthur, Robert S. Gilmore, Homer H. Glascock, II
  • Patent number: 4937203
    Abstract: The utilization of a removable overlay layer together with its associated metallization pattern, is used to effectively provide wafer scale integration for integrated circuit chips. The method and configuration of the present invention provide for the fabrication and testing of systems which are otherwise untestable. The present invention also permits integrated circuit systems to be tested in their final configuration in terms of speed and operating environment and the invention eliminates many of the problems associated with wafer or chip probes. The present invention also utilizes special test chips which are either temporarily or permanently affixed in an integrated circuit chip package.
    Type: Grant
    Filed: September 29, 1989
    Date of Patent: June 26, 1990
    Assignee: General Electric Company
    Inventors: Charles W. Eichelberger, Robert J. Wojnarowski, Kenneth B. Welles, II
  • Patent number: 4933042
    Abstract: A method and apparatus are provided for disposing a polymer film on an irregularly-shaped substrate at relatively high temperatures. In particular, the method and apparatus of the present invention provide a system for the packaging of very large scale intergrated circuit chips. The system of the present invention particularly solves problems associated with high temperature processing and problems associated with the highly irregular surfaces that result. Nonetheless, the resultant product is capable of being fashioned into circuit chip systems which are independently testable and which may be reconfigured after testing by removal of the polymer film itself.
    Type: Grant
    Filed: August 30, 1988
    Date of Patent: June 12, 1990
    Assignee: General Electric Company
    Inventors: Charles W. Eichelberger, Robert J. Wojnarowski, Kenneth B. Welles, II
  • Patent number: 4933740
    Abstract: An improved lateral insulated gate transistor includes a dual function anode and employs specially configured anode and cathode regions within the drift layer to promote lateral current flow. A vertical diode is disposed between a substrate cathode and anode of the device. Under forward bias conditions, the device exhibits insulated gate controlled conduction, and under reverse bias conditions, the device exhibits conduction between the substrate cathode and anode of the vertical diode.
    Type: Grant
    Filed: September 9, 1988
    Date of Patent: June 12, 1990
    Assignee: General Electric Company
    Inventors: Bantval J. Baliga, Andrew L. Robinson