Abstract: A monolithically integrated reverse conducting lateral insulated gate semiconductor device includes an inherent four layer structure which supplies a sufficient base drive to turn on an inherent lateral transistor under forward bias conditions. Under reverse bias conditions, an inherent five layer structure is activated to provide for high current density low voltage reverse conduction in the device. Forward and reverse current flow can be interrupted by the application of an appropriate bias to the same insulated gate electrode. The disclosed semiconductor device achieves improved current density and concomitantly reduced cell size.

Abstract: A multistage amplifying thyristor incorporates integral current control resistor regions between adjacent thyristor stages for limiting turn-on current in all but the main thyristor stage. The thyristor is essentially immune from di/dt turn-on failure without the need for external circuitry to limit di/dt in the thyristor. Modulation of the current control resistor region during turn-on is prevented by adequately spacing or shielding the region from the emitter of each thyristor stage as well as by adequate spacing or shielding of the resistor region from a portion of the lowermost emitter region containing a turn-on plasma of the preceding thyristor stage.

Abstract: A semiconductor hermetic package for semiconductor device comprises base, sidewall and cover members. Signals can be coupled between the enclosed devices and external devices by coupling means including conductive regions disposed in and through the package. Light pipes or conductive tracks and paths extending through the package can be used to couple the signals. A portion of the package can function as a grading resistance.

Abstract: A synchronous rectifier is able to operate at higher frequencies and provides an output having lower noise than prior art FET synchronous rectifier system by using field effect switching devices which contain only one conductivity type of semiconductor material and connecting a high speed, low charge storage diode in parallel. Schottky diodes are preferred whereby there is no junction diode in the structure. Conventional FETs may be used when paralleled with a Schottky diode which prevents the FET's parasitic internal diode from becoming conductive.

Abstract: An IGBT and FET are integrated in a common semiconductor body and share common source/emitter, base and drift regions and an insulated gate electrode. The ON-resistance and turn-off time of this device can be controlled by connecting the drain and collector electrodes to one main terminal for the device with a resistor between either the drain region/drift region interface or the collector junction and the main terminal of the device.

Abstract: A method of forming a multilayer metallization pattern using siloxane polyimide dielectric layers comprises forming the first siloxane polyimide layer, laser etching holes in the first layer, plasma etching the first layer to be sure the holes are clean, then cleaning the surface of the first layer in an etchant for silicon oxide, after which the metallization layer is formed and patterned and a second siloxane polyimide layer is formed thereover with good adhesion.

Abstract: In order to solve the problem of the proximity effects which occurs in the fabrication of integrated circuit devices, a facile method is provided for automatically creating a new pattern in which variably spaced windage correction is applied over the mask. This permits the utilization of conventional design fabrication rules and systems without the concomitant problem of producing small feature sizes in isolated structures. The method produces highly desirable chip masks and is readily implemented on commercially available CAD systems presently being employed for the production of circuit masks. The method is automatic and extremely easily implemented.

Abstract: A power switch which comprises a plurality of contact pairs connected in series provides substantial operational advantages. Included in these advantages are fast operating speed and direct imposition of circuit opening. The individual contact pairs are preferably controlled by piezoelectric benders to provide a compact, lightweight switch.

Abstract: A monolithically integrated lateral semiconductor device preferably comprising a pair of inherent transistors driven by an inherent lateral four layer structure is disclosed. The disclosed device includes inherent vertical and lateral bipolar transistors. An inherent lateral four layer structure is also included within the device to provide a sufficient base drive to fully turn on both the lateral and vertical inherent bipolar transistors. The lateral four layer structure can be controlled through an insulated gate.

Abstract: A self aligned method of fabricating a self aligned semiconductor device employs an initial step in which a first window having an inner perimeter and outer perimeter is opened through a first protective layer situated atop a semiconductor substrate, to divide the substrate into three separate zones. The window exposes a first surface portion of the semiconductor substrate and circumferentially defines or encompasses a second central portion of the protective layer as well as a second unexposed surface portion of the substrate. A third surface portion of the substrate lies beyond the outer perimeter of the first window. Precisely aligned substrate regions of the same or different conductivity type can be established by using differentially etchable materials to mask designated surface portions of the substrate.

Abstract: The utilization of a removable overlay layer together with its associated metalization pattern, is used to effectively provide wafer scale integration for integrated circuit chips. The method and configuration of the present invention provide for the fabrication and testing of systems which are otherwise untestable. The present invention also permits integrated circuit systems to be tested in their final configuration in terms of speed and operating environment and the invention eliminates many of the problems associated with wafer or chip probes. The present invention also utilizes special test chips which are either temporarily or permanently affixed in an integrated circuit chip package.

Abstract: A laser, such as an excimer laser, is employed to ablate electroless plating activator material from polymer and other substrates. The treated substrates are then immersed in electroless plating baths for plating of conductive material over remaining activator material. The method is particularly effective for depositing conductive patterns on non-flat substrates and on substrates needing plated-through connections. High resolution patterns are created on any compatible polymer substrate with any compatible electroless plating activator material.

Abstract: A switching matrix includes at least one array of piezoelectric relays whose cantilevered drive elements are in the form of a unitary, comb-shaped structure of the piezoceramic mateial. Each drive element carries adjacent its free end at least one movable contact for engagement with one or more fixed contacts in either single or double throw fashion. The movable contacts may be mounted on housing walls enclosing the relay array or on a separate substrate also mounting the drive element unitary structure. Row and column conductors or conductor pairs are connected into the relay contacts by non-intersecting conductor runs printed on the surfaces of the housing walls or on the substrate.

Abstract: An integrated circuit with a substrate of one conductivity type and a drift layer on the substrate of opposite conductivity type includes a high voltage semiconductor device, such as a P-N diode, with a first main device region of the opposite conductivity type adjoining the drift layer and a second main device region of the same conductivity type as the substrate adjoining the drift layer. The high voltage semiconductor device is electrically isolated from other devices through the incorporation into the integrated circuit of an isolation region adjoining the substrate and surrounding the high voltage device. Electrical isolation of the high voltage device from the substrate is achieved by interposing a highly-doped buried layer of the opposite conductivity type between the second main device region and the substrate so as to prevent current carrier injection from the second main device region into the substrate.

Abstract: A semiconductor wafer having a substrate with an epitaxial layer thereon includes a semiconductor device electrically isolated from the substrate as well as from any other devices in the wafer by electrical isolation structure comprising semiconductor material. The semiconductor device can accordingly be operated at high voltage with respect to the wafer substrate. The isolation structure in one form of the wafer comprises an N+ high voltage tub included in the wafer and a P+ ground region situated in the expitaxial layer, adjoining the substrate, and horizontally circumscribing the N+ high voltage tub and being spaced therefrom by a minimum layer extent of a portion of the epitaxial layer that is of N conductivity type.

Abstract: Lateral MOS controlled gate turn-off triacs with large OFF-Gate-width to emitter-width ratios. In one embodiment an ON channel is provided at one main electrode and an OFF channel is provided at the other. In another embodiment two channels in a series are provided at each main electrode. Current turn-off capacity is increased by serpentine or comb shaped channel regions or by trenches which provide channels along their walls.

Abstract: The present invention relates generally to monolithically integrated insulated gate semiconductor devices and more particularly to an improved structure which provides for high current density, low voltage drop conduction in both forward and reverse directions. More particularly, a single insulated gate device can initiate and interrupt current flow in both the forward and reverse directions.

Abstract: Polyimides, polycarbonates, polyetherimides and other highly stable organic polymers are photoetched through the use of deep ultraviolet light produced by a broad area, non-coherent, continuous light source. This method is effective in an oxygen-free environment, but provides slightly higher etch rates in an air ambient as a result of the oxygen in the air ambient. The apparatus in which this photoetching occurs may employ a single light source or a plurality of side-by-side lamps and may include ports which allow continuous transport of samples therethrough.

Abstract: A monolithically integrated semiconductor device preferably comprising a thyristor driven transistor is disclosed. The thyristor provides a base drive sufficient to fully turn-on an inherent bipolar transistor and achieve the maximum benefit of bipolar conduction within the semiconductor device. The thyristor can be turned on and off through insulated gate control by decoupling the emitter region of the thyristor from the cathode electrode of the device.

Abstract: An adaptive method and system are disclosed for providing high density interconnections of very large scale integrated circuits on a substrate. The procedure is performed in four basic steps: first an artwork representation for the interconnections of the integrated circuits is generated. This artwork representation is stored in a computer data base and assumes the integrated circuits to be at predetermined ideal locations and positions on the substrate. Second, using imaging, the actual positions of each integrated circuit on the substrate are determined. The actual positions of the integrated circuits are compared with their ideal positions to compute an offset and rotation for each integrated circuit on the substrate. Third, the computed offsets and rotations are then used to modify the artwork representation stored in the data base to account for the actual locations and positions of the integrated circuits on the substrate.