Abstract: A method of providing a unitary body comprised of two initially separate layers having similar coefficients of thermal expansion involves forming a mat of glass fibers in a configuration suitable for bonding the two layers together, placing the glass mat between them and heating the resulting stack to a temperature at which the individual fibers of the glass mat deform to form a continuous layer of glass which adheres to both layers, after which the stack is cooled to result in the unitary body.

Abstract: An MOS gate turn-off thyristor structure includes non-regenerative (three-semiconductor-layer) portions interspersed with four-semiconductor-layer regenerative (thyristor) portions, gate electrode segments disposed adjacent to relatively narrow portions of the base region within the regenerative portion, and either ohmic contacts or Schottky barrier contacts to the non-regenerative portions. Upon application of an appropriate turn-off gate bias to the gate electrode segments, the base region of the regenerative portion in which they are disposed is pinched off and the current flowing therethrough is derived to flow through the non-regenerative portion of the structure. This interrupts regeneration in the regenerative structure and the device turns off.

Abstract: A method compatible with very large scale integrated circuit fabrication processes is employed to provide an electrical connection between conductive layers separated by an insulative layer in integrated circuit devices. An intermediary metal such as molybdenum or tungsten is deposited by one or more methods so as to fill an opening in the insulative layer. A planarization resist may be applied on the substrate and the resulting configuration is planarizingly etched down to the insulative layer so as to provide a metal plug conductive layers. Deposition is by sputtering, evaporation, or by either selective or non-selective chemical vapor deposition. The process and structure provided herein significantly alleviates step coverage problems associated with aluminum and like materials which do not readily penetrate small VLSI circuit openings.

Abstract: A power field effect device has a high voltage blocking junction which intersects the device surface under the gate electrode. That intersection is a closed plane geometric figure whose center is within the body region of the device rather than in the more heavily doped base region of the device. The figure preferably is everywhere convex and has a maximum width of substantially less than the depletion width, at breakdown, of a corresponding parallel plane junction. The device breakdown voltage is higher than the breakdown voltage of a corresponding junction having a cylindrical edge with a straight axis. In a preferred embodiment, the high voltage blocking junction has a plurality of such intersections with the device surface, each situated beneath a segment of the gate electrode. In a bipolar embodiment, the gate electrode may be omitted.

Abstract: An improved insulated gate semiconductor device is provided with an extra short grid region of one type conductivity disposed proximate the PN junction between the first and second regions of the device. The extra short grid region provides an alternate path for one type conductivity carriers to inhibit forward biasing of the PN junction between the first and second electrodes. In addition, the grid allows opposite type conductivity carriers to flow therethrough. A portion of the grid is spaced and separated from the first region. Accordingly, a device fabricated in accordance with the present invention is less susceptible to latching and exhibits a higher voltage latching threshold.

Abstract: A semiconductor device comprises four regions of alternating conductivity type and comprises a plurality of turn-on cells at one of its major surfaces and a plurality of turn-off cells at another of its major surfaces. Both the turn-on and turn-off cells are of the conductor-insulator-semiconductor type. In an embodiment, the cell repeat distance for both turn-on cells and turn-off cells is preferably less than about the minimum thickness of the region of the semiconductor device that supports most of the device voltage. This enables the semiconductor device to operate efficiently in a field-effect transistor mode, in addition to a thyristor mode.

Abstract: Insulated-gate semiconductor devices, such as MOSFETs or IGTs, include an implant shorting region adjoining both base and source regions with the implant shorting region being conductively coupled to the source electrode so as to implement a base-to-source electrode short. The implant shorting region can be formed without a specially-aligned mask by utilizing the gate electrode as an implant mask.

Abstract: A ceramic chip carrier comprising a ceramic substrate and a copper lead frame directly bonded to the substrate, the lead frame being formed to provide leads in fringe regions beyond the edges of the substrate which are connected together by a removable rim and adapted to be suitably formed to make electrical and mechanical contact with the conductive runs on a printed circuit board.

Abstract: A power field effect device has a gate grid having a plurality of elongate openings therein through which a base region forming a high voltage blocking junction with the underlying body was diffused. The openings have round ends in order to prevent the formation of spherical portions in the high voltage blocking junction. The round ends of adjacent openings are positioned close enough to each other that their diffusion regions merge, thereby raising the device breakdown voltage to that of the cylindrical junction portion along the straight edges of the junction. In an alternative embodiment, the openings do not have round ends and are positioned close enough together that their diffusions merge end to end.

Abstract: The present invention relates generally to monolithically integrated gate semiconductor devices and more particularly, to improved semiconductor structures in which the parasitic four layer structure has been modified to avoid the possibility that non-preferred turn-on can occur. The length of the emitter region is reduced to thereby reduce the length of the base emitter junction and the magnitude of the IR voltage drop than can occur along that junction. Further, high density shorts are provided along that junction to prevent the parasitic four layer structure from functioning in a non-preferred latched or regenerative conducting mode. In an alternate embodiment, the parasitic four layer structure has been eliminated. Accordingly, insulated gate control of the device is preserved.

Abstract: An MOS gate turn-off thyristor structure includes non-regenerative (three-layer or transistor) portions interspersed with the four-layer regenerative (thyristor) portions and further includes gate electrode segments disposed adjacent to relatively narrow portions of the base region. Upon application of an appropriate turn-off gate bias to the gate electrode segments, the base region of the regenerative portion in which they are disposed is pinched off and the current flowing therethrough is diverted to flow through the non-regenerative portion of the structure. This interrupts regeneration in the regenerative structure and the device turns off.

Abstract: A lateral charge control semiconductor device is disclosed wherein a plurality of gate filled trenches are disposed in side-by-side relation within a partially processed semiconductor wafer to define finger portions of a drain region therebetween. A field plate is disposed on the upper surface of the finger portions and a portion of the partially processed wafer is situated beneath the finger portions. Charge control can thus be provided to all surface of the finger portion of the lateral device to maximize the amount of charge control which can be applied to the device. More particularly, the carrier concentration within the finger portion can be increased to reduce the one-resistance of the device during forward conduction, while in a reverse blocking operation, lateral charge control can be applied to couple to the electric field originating with the ionized impurities situated in the drift/drain region to increase the breakdown voltage of the device.

Abstract: A solar array structure for use with satellites requiring large areas of solar arrays. Each array is a single continuous structure having continuous longitudinal members which in a stowed condition enable the panel to be wrapped around the satellite within its launch vehicle. In a deployed configuration, the longitudinal members are reconfigured to provide substantially increased stiffness in the direction of winding.

Abstract: A power semiconductor device incorporates in its active, or current-carrying, region a main current section and an emulation current section. The active region is surrounded by a common device termination region. This is accomplished through provision of respective separate cathodes for the main and emulation current regions, while the device anode is common to both the main and emulation current sections. The current level in the emulation current section provides an accurate representation of the current level in the main current section since the main and emulation current sections are closely coupled both thermally and electrically and, further, are formed in the same fabrication process. The current level in the main current section can be economically determined with low power circuitry by way of sensing the current level in the emulation current section.

Abstract: A semiconductor device comprising a bulk substrate and an epitaxial layer grown thereon attains the feature of rapid removal of majority carriers from an N-type active base region thereof, a function conventionally performed by anode shorts, through the incorporation into the otherwise P-type substrate of a highly doped, N-type region having a surface in contact with the N-type epitaxial layer for injecting majority carriers from an N-type active base region in the epitaxial layer into the remaining P-type portion of the substrate.

Abstract: A hybrid integrated circuit chip package is disclosed which includes a hybrid, low loss, multilayer metallization, silicon printed wiring board as an interconnecting, two-sided module to reduce the length of interconnections between integrated circuit chips positioned on opposite sides of the module.

Abstract: Solder layers in a semiconductor chip package, which electrically interconnect conductors used to gain electrical access to the electrodes on the semiconductor chip, are subjected to a transverse compressive force in excess of about 2 pounds per square inch. The semiconductor chip package can thereby undergo a marked increase in the number of cycles of heating and cooling before it fails due to increased thermal resistance arising from structural degradation of the solder layers.

Abstract: A method for depositing gold bumps on metallized pads of semiconductor chips uses a commercially available thermocompression or thermosonic gold wire bonder. The method includes the steps of depositing a gold ball with an attached wire on the metallized pad, and removing the wire so that a gold bump remains on the pad.

Abstract: Rare-earth-doped, polycrystalline yttria-gadolinia ceramic scintillators with high density, optical clarity, uniformity, cubic structure and which are useful in the detection of x-rays, include one or more of the oxides of rare earth elements Eu, Nd, Yb, Dy, Tb, and Pr as activators. The ceramic scintillator may also include CaO, SrO, and Yb.sub.2 O.sub.3 as afterglow reducers. Sintering, sintering combined with gas hot isostatic pressing, and hot pressing methods for preparing the ceramic scintillators are also described.

Abstract: A hermetically sealed package for a power semiconductor wafer is provided comprising substantially entirely silicon materials selected to have coefficients of thermal expansion closely matching that of the power semiconductor wafer. A semiconductor wafer such as a power diode comprises a layer of silicon material having first and second device regions on respective sides thereof. An electrically conductive cap and base, each including a layer of silicon material, are disposed in electrical contact with the first and second regions of the semiconductor device, respectively. An electrically insulative sidewall of silicon material surrounds the semiconductor wafer, is spaced from an edge thereof, and is bonded to the cap and base for hermetically sealing the package. An electrical passivant is disposed on an edge of the semiconductor wafer adjoining the first and second device regions for preventing electrical breakdown between the cap and base.