Patents Represented by Attorney Robert S. Bramson
  • Patent number: 5362942
    Abstract: A battery heater uses the internal resistance of the battery as the battery heating element. In one embodiment, a DC battery charger and a programmable battery load, is used in a closed loop temperature control system. In another embodiment, a DC battery charger and a resistor or small auxiliary battery heater, is used in a closed loop temperature control system. The programmable load or the small auxiliary battery heater, is enabled during full charge, low temperature conditions. The resistor or small auxiliary heater serves to both heat the battery and draw down the battery charge. In yet another embodiment, an AC heater power supply and a DC battery charger, is coupled to the battery in a closed loop temperature control system.
    Type: Grant
    Filed: August 24, 1993
    Date of Patent: November 8, 1994
    Assignee: InterDigital Technology Corporation
    Inventors: William T. Vanderslice, Jr., Christopher J. Scafidi
  • Patent number: 5333191
    Abstract: A method of operating a digital signal processor to detect DTMF tones in a digital voice telephone system in which the digitally encoded signals appearing on the telephone channel are decimated to compress the spectrum to be monitored for the appearance of call signalling tones. The signals received in a decimated block are "correlated" or convolved with one another on a forward and backward time-shifted basis and each forward and backward correlation product is summed to form the elements of a 5.times.5 modified covariance matrix. The modified covariance matrix exhibits the desirable property that its eigenvectors will be symmetric. Since all eigenvectors of the modified covariance matrix are orthogonal and the eigenvectors associated with the signal span the signal subspace, the signal subspace is orthogonal to the eigenvector associated with the noise. The dot product of the noise eigenvector with the signal subspace is set to zero.
    Type: Grant
    Filed: April 22, 1993
    Date of Patent: July 26, 1994
    Assignee: InterDigital Technology Corporation
    Inventor: Brian M. McCarthy
  • Patent number: 5326959
    Abstract: A computer-controlled funds processing and remittance processing system, for use by individual, business and other bank customers. The system eliminates the problems associated with batch processing of remittances and remittance advices in lockbox systems. Each participating bank receives, from each participating customer, identifying information regarding bills that are to be paid for that customer with the automated system. After initially collecting all necessary data regarding a participating customer's bills, the bank produces a paper form, which is manually completed by the customer, on a periodic basis. The customer manually inserts the amount to be paid for each bill being processed by the system, opposite pre-printed indicia indicating the identity of the payee. The resulting customer payment instruction document is delivered to the bank, and is optically scanned, to read the specific amounts to be paid for the respective bills.
    Type: Grant
    Filed: August 4, 1992
    Date of Patent: July 5, 1994
    Inventor: Justin J. Perazza
  • Patent number: 5111390
    Abstract: A computer system which uses a main processor with main memory, and operates under a specialized software operating system, provides for checking the integrity of its compiler by use of software routines which permit an authorized user or an authorized program to authorize a file as a compiler and additionally will operate to identify any ordinary user and ordinary programs so as to prevent such ordinary user or ordinary program from authorizing a code file as a compiler.
    Type: Grant
    Filed: August 22, 1988
    Date of Patent: May 5, 1992
    Assignee: Unisys Corporation
    Inventor: Larry R. Ketcham
  • Patent number: 5006787
    Abstract: An application specific integrated circuit is provided on a chip where a combinatorial logic circuitry such as a RAM memory array, logic circuitry and control circuitry may be operated in the normal mode with the addition of a built-in, self-test feature whereby the registers can be converted to multifunction shift registers which are connected in a serial fashion to form a shift chain snake through which data patterns can be shifted. Additionally, control circuitry is provided to select certain multifunction shift registers as test pattern generators and other multifunction shift registers are receivers of signatures which can be accessed by a maintenance controller to check proper operability of the system and its combinatorial logic.
    Type: Grant
    Filed: June 12, 1989
    Date of Patent: April 9, 1991
    Assignee: Unisys Corporation
    Inventors: Haluk Katircioglu, John A. De Beule, Debaditya Mukherjee
  • Patent number: 4995693
    Abstract: An optical switch for coupling one of a plurality of input light sources to one of a plurality of output terminals is comprised of a Bragg cell array acoustically excited in accordance with one or more preselected control frequencies from a selectable source of such frequencies. The beam deflection is proportional to the applied radio frequency. A scan lens is positioned to intercept the deflected beams and to focus the beams into a plane for imaging upon a linear array of optical output fibers. By choice of the control frequency any combination of input and output fiber optic lines may be optically coupled without requiring active sensors. Sufficient diffraction is provided by the Bragg cell in combination with the scan lens to minimize cross-talk and insertion loss.
    Type: Grant
    Filed: August 5, 1988
    Date of Patent: February 26, 1991
    Assignee: Unisys Corporation
    Inventor: Mark L. Wilson
  • Patent number: 4996688
    Abstract: Apparatus for detecting and isolating the occurrence of faults in a digital electronic system so as to reduce the mean-time-to-repair. Associated with the logic circuitry to be monitored is a fault indicator which produces a fault signal when a malfunction occurs. Fault capture circuitry is arranged in a hierarchical manner and provides a group fault output signal when one of the fault indicators generates a fault signal. A programmable controller is provided which receives the group fault signal as an interrupt and which then responds by transferring registered fault event signals to a dynamic string register, rearming the error detection used to trap a fault signal and logging the fault location in a memory for later readout by a maintenance processor or the like. The dynamic string allows communications to take place using a scan/set protocol.
    Type: Grant
    Filed: September 19, 1988
    Date of Patent: February 26, 1991
    Assignee: Unisys Corporation
    Inventors: Larry L. Byers, Kay Tsang, James H. Scheuneman, Penny Svenkeson
  • Patent number: 4977495
    Abstract: A system for maintaining a cache in the main memory of a large data processing system for storing many tracks of data received from a large number of disk files where the disk files are non-volatile which is required to store critical customer data. More importantly, the present invention resides in a software system which is a part of the operating system of a large data processing system to maintain this cache.
    Type: Grant
    Filed: February 29, 1988
    Date of Patent: December 11, 1990
    Assignee: Unisys Corporation
    Inventors: William Stratton, Carol Wellington
  • Patent number: 4970419
    Abstract: Transmission line termination circuitry is provided on a driven IC chip utilizing active transistors constructed and arranged so as to steer appropriately directed damping currents into the input bus in a manner which effectively minimizes both overshoot and undershoot without making undue demands on the normally provided chip power supply.
    Type: Grant
    Filed: March 23, 1987
    Date of Patent: November 13, 1990
    Assignee: Unisys Corporation
    Inventors: Timothy P. Hagen, Paul G. Tumms
  • Patent number: 4969160
    Abstract: Apparatus is provided for detecting the presence of a periodically keyed random modulated signal source. Received signals are stepped down to an intermediate frequency and then applied to pairs of narrow bandpass filters. The output from pairs of the narrow bandpass filters are applied to mixers to provide difference frequency signals occurring at the clock rate of the periodically keyed random modulated signal. The clock signal is processed through recovery circuits including a detector and a comparator A signal is generated at the output of the comparator when the clock signal is detected above the background noise and interference, thus, indicating the presence of a periodically keyed random modulated signal source.
    Type: Grant
    Filed: August 16, 1982
    Date of Patent: November 6, 1990
    Assignee: Unisys Corporation
    Inventor: Samuel C. Kingston
  • Patent number: 4965830
    Abstract: Apparatus for analyzing distortion levels of samples which occur in data compression systems of the type that may be integrated into a data compression system or used as a stand alone analyzer. The apparatus includes a processor that is coupled to the data compression system to provide the distortion analyzing apparatus with necessary input bit allocation and power level data for each sample. Memory storage is coupled to the processor for supplying predetermined unique quantization error values corresponding to each transform coefficient representing samples of digital data in a frame of digital data to be compressed.
    Type: Grant
    Filed: January 17, 1989
    Date of Patent: October 23, 1990
    Assignee: Unisys Corp.
    Inventors: Steven T. Barham, Michael J. Hurst
  • Patent number: 4964964
    Abstract: An electroplating rack is constructed of corrosion resistant stainless steel, with oppposed side frames milled with vertical channels to accommodate opposite side edge portions of a printed circuit board for plating. Mechanical and electrical connections with the circuit board are made with recessed stainless steel screws with rounded tips. Current is provided to the top of the rack, and also to the bottom of each side frame through an elongate, vertically disposed copper bar surrounded by an insulative sheath and contained within each side frame. Each of the copper rods is threadedly engaged in a steel end cap at the bottom of the associated frame. The current fed into the top and bottom of the rack can be adjusted by adjusting the comparative conductivity of the two paths.
    Type: Grant
    Filed: April 3, 1989
    Date of Patent: October 23, 1990
    Assignee: Unisys Corporation
    Inventor: Timothy I. Murphy
  • Patent number: 4964063
    Abstract: Conceptual structures which can be used to represent any knowledge that can be represented by frames/units. Its realization, in a software program called Unit Interface, provides a method of storing frame/unit data in conceptual structures and algorithms for accessing that data when stored in conceptual structures as if it were a frame/unit or collection of them.
    Type: Grant
    Filed: September 15, 1988
    Date of Patent: October 16, 1990
    Assignee: Unisys Corporation
    Inventor: John W. Esch
  • Patent number: 4963425
    Abstract: A laminated printed wiring board having surfaces thereof fabricated from conventional fiber reinforced laminates which are secured together by means of an adhesive fabricated of a reinforced thermosetting resin having a coefficient of thermal expansion (CTE) which is substantially smaller than the CTE of the surface laminate whereby the apparent CTE of the overall printed wiring board assembly is substantially controlled.
    Type: Grant
    Filed: March 5, 1985
    Date of Patent: October 16, 1990
    Assignee: Unisys Corporation
    Inventors: Alan M. Buchanan, Jay S. Abramowitz, Roberta A. Y. Flygare
  • Patent number: 4962508
    Abstract: In a receiving apparatus for detecting the presence or absence of periodically keyed random modulated signals, there are provided a pair of separate and distinct detection channels. One channel produces a real signal having clock line components and the other channel produces a decorrelated imaginary signal having no clock line components. The real and imaginary signals having carrier wave interference signals are processed in a Fourier transform device and a post processor to cancel out the carrier wave interference signals and to provide only a clock signal output when periodically keyed random modulated signals are being received.
    Type: Grant
    Filed: September 18, 1986
    Date of Patent: October 9, 1990
    Assignee: Unisys Corporation
    Inventor: Samuel C. Kingston
  • Patent number: 4962501
    Abstract: A plurality of transmitting and receiving elements are coupled between read and write buses. The communication paths which connects the tranmitting and receiving elements to the buses are each provided with a fault indicating circuit in series therewith. Each of said fault indicating circuits have logic gating means which include a bit register for each of the bits of a data byte and a parity bit. The output of the bit register means are coupled to isolation drivers which in turn are connected to parity checking circuits and the buses for indicating errors which occur in the bytes of a data word without degrading or delaying data transmission to and from said read and write buses.
    Type: Grant
    Filed: September 13, 1988
    Date of Patent: October 9, 1990
    Assignee: Unisys Corporation
    Inventors: Larry L. Byers, James H. Scheuneman, Joseba M. Desubijana
  • Patent number: 4959749
    Abstract: A layered electronic assembly contains a plurality of integrated circuit chips that are arranged in a stack; respective adhesive layers interleave the chips and hold them together; and I/O leads on the chips extend to one face of the stack. Also, the chips in the stack have respective thicknesses which vary from chip to chip; the I/O leads are offset from one edge of the chip on which they lie by respective distances which vary from chip to chip; the adhesive layers in the stack have respective thicknesses which compensate for the thickness variations in the chips such that the I/O leads on adjacent chips are spaced by predetermined distances along the stack face; and the chips are shifted relative to one another such that their one edge is misaligned while their I/O leads are aligned on the stack face. This layered electronic assembly uses 100% of the electrically functional chips which are cut from a semiconductor wafer without sacrificing any accuracy with which the I/O leads are aligned on the stack face.
    Type: Grant
    Filed: August 16, 1989
    Date of Patent: September 25, 1990
    Assignee: Unisys Corporation
    Inventors: John E. Dzarnoski, Jr., James W. Babcock
  • Patent number: 4956644
    Abstract: A signal detector for receiving a wide band (W) of frequency-hopped signals which channelizes the incoming signals, via filter banks into a plurality (L) of channels. Magnitude squaring circuits in each channel generate a "power" estimate which is compared to a preset threshold value by threshold-quantizer units that produce a positive voltage (=1) if the threshold is exceeded. After summation of all the channels, the direct sequence (DS) signal component and noise component are processed so that a DC voltage is produced if a frequency-hop signal (FH) is present which is greater in value than when the signal is not present. Thus the DC signal indicates whether the FH signal is present or absent.
    Type: Grant
    Filed: October 4, 1989
    Date of Patent: September 11, 1990
    Assignee: Unisys Corporation
    Inventors: Ronald S. Leahy, Patrick J. Smith, Scott R. Bullock
  • Patent number: 4954996
    Abstract: A simulator of bottom return signals for a sonar system on a moving ship generates pulsed frequency modulated signals to simulate ocean bottom returns. Signals from the sonar transmitter are stretched in accordance with a postulated bottom configuration and applied to the frequency modulators to provide frequency modulated signals for the duration of the stretched pulses. Noise is simulated with the addition of an appropriate sinusoidal signal to each pulsed frequency modulated signal.
    Type: Grant
    Filed: May 15, 1989
    Date of Patent: September 4, 1990
    Assignee: Unisys Corporation
    Inventors: Luciano Fazzolari, Frank P. Giattini, Anthony L. Scoca, Eugene C. Zavacki
  • Patent number: RE33461
    Abstract: A timing generator and verifier is provided in which a PROM stores the timing constants that are employed by the generator. An address counter, which is driven by a clock timer, cycles through an associated portion of the PROM to provide a sequence of output signals which represent timing for a particular mode. If a different mode is selected, the address counter selects a different sequence of output bits. During Normal mode the address counter operates on a cyclic basis driven by a fixed frequency free running master clock. In Verify mode the address counter is stepped by the Host computer. The outputs of the PROM are coupled through a buffer and logic section, where the outputs may be modified before being coupled to an adder which accumulates a checksum based on the outputs of all of the bits for a particular selected timing.
    Type: Grant
    Filed: May 18, 1989
    Date of Patent: November 27, 1990
    Assignee: Unisys Corporation
    Inventors: Katherine A. Splett, Steven H. Karban, Gerald L. Brown