Abstract: Logic checking circuits are provided for verifying whether or not the data bus enable logic circuits are operating properly in response to operational commands to transmit or to NOT transmit data. The transmit latches in the bus interface logic circuits are continuously monitored to determine if they are set or NOT set in a position to enable transmission of data or NOT to enable transmission of data to a bus. Transmit gating circuit means are couple to the output of said transmit latches for determining if all of the transmit latches are in the same state and are in the state ordered by the central controller, and for determining whether the state ordered by the central controller occurs in the exact time period during which the command to transmit should be executed.

Abstract: A full bridge switching power converter employs zero-voltage, resonant-transition (ZVRT) switching techniques which appreciably reduces the switching losses at high switching frequencies, (for example, 1 MHz and above), using constant frequency, pulse-width-modulation techniques. The converter is implemented using a transfer with four switching FET's coupled to the primary of the transformer and four switching FET's coupled to the output of the transformer and a control unit that supplies the constant waveforms necessary to achieve synchronization and timing required to achieve the ZVRT switching.

Abstract: A novel unconditional clock and automatic refresh logic system is provided which comprises a source of unconditional clock pulses coupled to the memory control logic in a manner which permits automatic refreshing of a dynamic memory. There is further provided clock logic means which sense the conditions in the dynamic memory system during which the dynamic memory is not being refreshed. There is further provided, means for generating automatic clock refresh signals coupled to the memory control logic for initiating continuous automatic refresh cycles when the system clock is being shutdown.

Abstract: A logic cell, for use in a semicustom chip, is comprised of a plurality of transistors that are integrated into a semiconductor substrate and are interconnected within the cell to perform a logic function. This cell has sidewalls which define the space in the chip which contains all the transistors and their interconnections within the cell; at least one of the sidewalls is shaped to include a step which gives the cell a narrow top and a wide bottom; and one or more of the cell's transistors lies below the step in the wide bottom of the cell. Many of these cells are arranged in spaced apart rows on the semicustom chip in which the narrow tops of the cell line up. Conductors which interconnect the cells are disposed in the space between the narrow tops of the cells and over the transistors in the wide bottoms of the cells. Using this architecture, the density with which a logic cell is integrated to a semicustom chip is improved more than 100%.

Abstract: A narrowband parameter estimator circuit is described which can be used to estimate the frequency and the relative power of narrowband interference tones which reside in a wideband information signal. A two-weight adaptive filter with a phase/frequency-lock loop circuit works in conjunction with a stepped synthesizer to lock onto the individual narrowband interference tones. A lock-detect circuit signals a digital logic unit to record the frequency of the stepped synthesizer and to measure the power in the adaptive filter output signal. This same output signal is used to cancel the unwanted tone in the wideband information signal being transmitted.

Abstract: The logic cards for a main storage unit or computer logic which receive request operations for access to portions of the memory or logic are divided into banks or elements. When a request operation attempts to access one of the elements a return busy signal is raised from that element. The present invention structure generates a predicted busy signal which occurs during the same time the return busy signal should be activated or operable. The return busy signal and predict busy signal are compared in novel circuitry to verify that the element performing the operaton is in fact performing an operation during the predetermined time slot allowed for performance of the requested operation. Fault signals for bank invalidation are stored in internal check trap circuitry for future reference when the requestor raises a subsequent request operation.

Abstract: A tightly coupled data processing system having high performance characteristics, including at least one general purpose host processor coupled to host processor ports of a High Performance Storage Unit, and a Scientific Processor directly coupled to scientific processor ports of the High Performance Storage Unit is described. The Scientific Processor is under task assignment control of the host processor and shares the same memory space as the host processor, and thereby provides the tight coupling without need of dedicated memory or caching. Provision is also made for the Scientific Processor to share the virtual address space of the host processor. A tightly coupled system is also disclosed wherein a plurality of general purpose host processors are each coupled to one or more High Performance Storage Units, and a Multiple Unit Adapter is utilized to couple an associated Scientific Processor to all of the High Performance Storage Units.

Abstract: A high-speed partitioned set associative cache memory is provided with a plurality of cache memory boards. Each of the boards is provided with a partial data array and a full tag array on each board. At least one memory address register is mounted on each of the boards with the partial data array and the full tag array for receiving a unique address from the central processing unit which enables the plurality of memory address registers to simultaneously access addresses in the partial data arrays on different boards and to also address tag addresses associated with the data addresses by sequencing controls mounted on a separate board with logic circuits which monitor output signals from the data arrays and the tag arrays. The output signals resulting from accessing memory locations in the cache memory are coupled to logic circuits for determining the type of error and the exact array where a single error has occurred.

Abstract: The present invention provides a novel dynamic vertical height control circuit for a CRT display which is adapted to receive an input signal over a broad range of variable frequencies. The dynamic variable input frequency is applied to a free running oscillator which is coupled to a ramp generator for producing a ramp output signal. The ramp output signal is coupled back through novel feedback means comprising a comparator and means for determining the magnitude of the ramp output signal voltage for producing a feedback signal which is applied as a control signal to the ramp generator. The feedback control maintains a vertical height control signal which maintains a constant vertical display size on the CRT display.

Abstract: Failures of duplicate input signals to two indentical electronic modules which may be units, cards, circuits or other entity, are detected by comparison. In each electronic module functional input signals are captured in a plurality of latches on different, or the same, clock phase. Each input signal is captured directly in latches on the same phase as the functional latch which used it to provide a plurality of link signals which are encoded by techniques, such as parity or residue encoding, and compared. The result of the link signal comparison is stored in a register. The outputs of the register are encoded and are supplied to a comparator which compares a signal from the other identical electronic modules. When miscomparison occurs location of the type of failue is facilitated by the system.

Abstract: A sheet handling mechanism adapted to receive processed documents (e.g., from a printer) in a holding receptacle secured within a machine which can either "dump" them or be shifted to present them to a user automatically when the user manipulates the access door of the machine (e.g., bin coupled to be pivoted when user raises door).

Abstract: A digital translator, on a semiconductor chip that contains N-channel transistors and P-channel transistors which have threshold voltages that vary about respective nominal values, includes an input/output module which is made of the transistors and which receives a digital input signal at two voltage levels and in response generates a digital output signal at two different voltage levels. To compensate for the threshold variations and thereby stabilize the voltage levels of the output signal, the translator also includes a voltage generator which produces a reference voltage for the input/output module.

Abstract: A hop rate detector, for receiving frequency-hopped signals carrying information data, which generates a tone at the "hop rate" when modulated or unmodulated frequency-hopped signals are present. The input signal is channelized into sub-bands via filter banks and the signal in each channel is power detected (squared) and compared to a present threshold to produce a positive voltage (="1") if the threshold is exceeded and zero volts (="0") otherwise. The channel signals are split into an upper band (B.sub.u) and lower band (B.sub.d), then each band is summed and the lower band sum subtracted from the upper band sum to provide a first stage signal. The first stage signal has its DC component removed, then is multiplied by a delayed copy of itself to provide a frequency tone indicating the hop rate of the received signal.

Abstract: A loosely coupled parallel network simulator has been described which employs a time multiplex bus to which a plurality of processing sites are coupled with each processing site being assigned one or more particular time slots during the bus cycle. Each processing site contains a sequencing RAM or control store which determines that clock time during the bus cycle that the processing site is to be given access for either transmission or reception of data segments.

Abstract: A multiple document detector set having a driven wheel and an opposed idler wheel for gripping documents in a pinch created there-between. The idler wheel (44) is provided with a slipping clutch (62) for creating a rotation opposing torque. The idler wheel (44) and the driven wheel (42) each have a coefficient of friction against documents greater than the coefficient of friction of documents against one another. When multiple documents are introduced into the nip (46) one document (32) is held by the idler wheel (44) and the other document (34) is driven by the driven wheel (42). A monitor (18) detects whether or not the driven wheel (42) has the same periphral velocity as the idler wheel (44) and signals the presence of multiple documents if the peripheral velocities are not the same. The monitor (18) signals completion of separation of multiple documents when the peripheral velocites once again become the same.

Abstract: A personal computer (PC) running on MS/DOS interactively and graphically creates or modifies definitions for print fonts, electronic forms, page compositions and sketches and includes a function for converting the definitions for transfer to a mainframe computer facility for use by the mainframe printer control function and printer. The PC further includes functions for creating or modifying character arrangements, EFORM arrangements, page composition arrangements and sketch arrangements where the arrangements include all of the components required to print the entity. The mainframe computer comprises an OS1100 system with PERCON for controlling a laser printer. The invention includes a function at the mainframe facility for converting the definitions transferred thereto from the PC into omnibus elements containing the data required by PERCON to print the entities. The omnibus elements are stored in a user library.

Abstract: A variable refractive index device, such as a Bragg cell, is temperature stabilized by sensing ray path deviations of a secondary diffracted beam. Two photodetectors with centers offset from the exit position of the central ray of the beam at normal temperature operation receive light energy as a function of the deviation of this ray path from the normal position. Light in each fiber is detected to derive electrical signals that are utilized to establish a correction signal to a voltage controlled oscillator which varies the frequency thereof and compensates for the diffraction deviations caused by temperature variations.

Abstract: In a system for electroplating a printed circuit board in which multiple spray orifices are provided in arrays on opposite sides of the circuit board, and multiple vacuum orifices are interspersed symmetrically and midway between adjacent spray orifices, a mounting means is provided for rapid and accurate locating of the printed circuit board in two selectively offset alternative positions to facilitate forming an electroplated layer of uniform thickness. The printed circuit board is supported from an elongate copper bar, with two alignment members mounted to opposite ends of the bar. A pair of saddles are fixed with respect to the tank containing the electrolyte. Each of the saddles has two V-shaped mounting surfaces conforming to the alignment members for a nesting engagement.

Abstract: A dynamic random access memory (DRAM) memory refreshing scheme utilizes at least two separate refresh channels. Each of the channels consists of a pair of identical counters which are coupled through two different types of timing chains. One of the timing chains is associated with one of the counters and generates a refresh request signal, while the other timing channel generates a refresh error signal. As long as the refresh error signal matches the refresh request signal, no error is present, and a validated refresh request signal will be generated from that timing channel and supplied to an OR gate to refresh all of the memory banks for the memory.

Abstract: Disclosed is a digital computer having memory means stacked on an insulating layer over a semiconductor substrate. In one embodiment, the memory means includes an array of diodes which overflies the substrate and generates control signals for an arithmetic section that lies in the substrate; and in another embodiment, the memory means includes N arrays of diodes which overlie the substrate and operate in parallel to generate signals representing arithmetic transformation of a portion of their address inputs.