Abstract: A complex integrated circuit comprises at least a plurality of modules coupled together through at least a system channel. The circuit further comprises a plurality of input/output devices for interfacing the circuit with structures outside the circuit. The plurality of input/output devices comprise at least a first circuit portion implemented as a module coupled to the remaining modules of the circuit by the first channel system (BUS1).

Abstract: The invention relates to a memory comprising memory cells arranged in continuous rows which are divided in at least two subrows separately selectable by a row decoder through respective word selection metallizations. Each word selection metallization extends over the row containing the corresponding subrow and the subrows of each row are interlaced.

Abstract: A method of depositing a dielectric ply structure to optimize the planarity of electronic devices that include a plurality of active elements having gate regions laid across the substrate as discrete parallel lines, such as the bit lines of memory cells. In accordance with the principles of the present invention, the plurality of bit lines may be isolated from one another by the dielectric ply structure to provide a planar architecture onto which an optional conductive layer may be deposited. The resulting planarization avoids the typical shortcomings of the prior art, such as the lack of electrical continuity in the word lines or their excessively high electrical resistance from slenderized portions in the conductive sections due to poor planarity of the surfaces upon which the conductive layer is deposited.

Abstract: An optical two-dimensional position sensor including a selective optical unit which faces, and is displaceable relative to, an integrated device. The selective optical unit is formed by a polarized light source and a filter with four quadrants which permits passage of light through two quadrants only. The selective optical unit is attached to a control lever such as to translate in a plane along a first direction and a second direction, and to pivot around an axis which is orthogonal to the preceding directions. In a transparent package, the integrated device comprises a first group of sensor elements which are spaced along the first direction, a second group of sensor elements which are spaced along the second direction and a third group of sensor elements which detect an angular position of the selective optical unit.

Abstract: A biasing device for biasing a memory cell having a substrate bias terminal associated therewith. The biasing device includes a first sub-threshold circuitry block adapted to supply an appropriate current during the device standby phase through a restore transistor connected between a supply voltage reference and the substrate bias terminal of the memory cell, and having a control terminal connected to a bias circuit, in turn connected between the supply voltage reference and a ground voltage reference to drive the restore transistor with a current of limited value.

Abstract: An integrated device for a switching system is disclosed. The device includes control circuitry for generating at least one switching control signal, reference circuitry for generating at least one reference quantity, a using circuit for using the reference quantity, a circuit for storing the reference quantity, and a switch which, in a first operative condition, connects the reference circuit to the using circuit and to the storage circuit in order to apply the reference quantity thereto. In a second operative condition, the switch disconnects the reference circuit from the using circuit and connects the storage circuit to the using circuit in order to apply the stored reference quantity thereto. Finally, the device includes filtering circuitry for keeping the switch in the second operative condition for a filtering period in accordance with the switching of the control signal.

Abstract: An EEPROM cell is described as having a screening metal structure formed of preference in the first metal layer and located in substantial overlaying relationship at the floating gate terminal. This defeats the possibility of anomalous readings being obtained by measuring the amount of charge on the floating gate terminal. An additional screening metal structure, to be formed in the third and following metal layers, may be provided to fully overlie the cell and provide additional protection against anomalous readings.

Abstract: A memory device has an array of memory cells, including at least one memory block including multiple-level memory cells adapted for storing each one N.gtoreq.2 bits of information. The at least one memory block also includes electrically erasable and programmable bilevel memory cells, each for storing one bit of information. A circuit is provided for either accessing and reading one of said multiple-level memory cell or simultaneously accessing and reading N of said electrically erasable and programmable bilevel memory cells, depending on address signals supplied to the memory device.

Abstract: The present invention relates to a voltage converting circuit adapted to being supplied by at least two rectified A.C. voltages of different levels, including at least two capacitors and a switching circuit to organize a parallel discharge of the capacitors, and to organize a series or parallel charge of the capacitors according to a supply voltage level.

Abstract: An integrated circuit including two phase-locked loops each with its own oscillator. To prevent locking owing to injection between the two oscillators due to stray currents in the integrated circuit, a noise generator is coupled to the oscillator of one of the loops and a timer is provided for activating the noise generator in a manner such that the noise generated changes the frequency of the oscillator randomly when the other loop is in operation.

Abstract: Embodiments of the invention provide a transconductance control circuit, particularly for a continuous-time filter, comprising a transconductor across which a constant voltage is input. The transconductor is connected to a digital-to-analog converter (DAC) to set a reference current. A feedback loop is provided between an output of the transconductor and an input. In particular, the circuit further comprises a means for mirroring the reference current set by the DAC both to the feedback loop and to at least one cell of a cascade-connected filter.

Abstract: A non-volatile memory cell and a manufacturing process therefor are discussed. The cell is integrated in a semiconductor substrate and includes a floating gate transistor having a first source region, first drain region, and gate region projecting over the substrate between the first source and drain regions. The cell also includes a selection transistor having a second source region, second drain region, and respective gate region, projecting over the substrate between the second source and drain regions. The first and second regions are lightly doped and the cell comprises mask elements.

Abstract: An analog read circuit includes an output transistor connected to a memory cell to be read, and an operational amplifier having a non-inverting input connected to the drain terminal of the memory cell, an inverting input connected to a reference terminal, and an output, forming the output of the reading circuit and connected to the gate terminal of the output transistor. Bias transistors maintain the memory cell and the output transistor in the linear region, and the operational amplifier and the output transistor form a negative feedback loop so that the output voltage V.sub.O of the read circuit is linerly dependent upon the threshold voltage the memory cell. The reading circuit has high precision and high reading speed.

Abstract: A test structure is formed by an array of memory cells connected in parallel and including each a memory transistor and a select transistor connected in series. The gate terminals of the select transistors of all memory cells are biased to a value next to the threshold voltage of the select transistors. Therefore, in each memory cell, the drain current is limited by the memory transistor for control gate voltages below the threshold voltage of the memory transistor, and by the select transistor at higher voltages; for high control gate voltages, the drain current is clamped to a constant maximum value. Since the clamping effect of the select transistors acts on each memory cell, the total maximum current of the test structure may be held below a value causing a limitation in the current generated by the entire array because of the resistance in series to the output of the test structure.

Abstract: A process creates contacts in semiconductor electronic devices and in particular on bit lines of non-volatile memories with cross-point structure. The cross-point structure includes memory cell matrices in which the bit lines are parallel unbroken diffusion strips extending along a column of the matrix with the contacts being provided through associated contact apertures defined through a dielectric layer deposited over a contact region defined on a semiconductor substrate at one end of the bit lines. The process calls for a step of implantation and following diffusion of contact areas provided in the substrate at opposite sides of each bit line to be contacted to widen the area designed to receive the contacts.

Abstract: A monolithic integrated device includes a protection structure and is formed in a semiconductor material substrate having a first conductivity type, which device includes at least a first epitaxial layer formed on the substrate. The integrated device further includes a bipolar first transistor formed of a base region having a second conductivity type and including a first buried region formed in the first epitaxial layer, and having a first diffused region which extends from the first buried region to contact a top surface of the integrated device through a surface contact region with a high concentration of dopant material. The first transistor also has an emitter region with the first conductivity type, embedded in the base region, and including a second buried region formed on the first buried region and a second diffused region, with a high concentration of dopant material, which extends from the second buried region to contact the top surface of the integrated device.

Abstract: A row decoder includes a plurality of pre-decoding circuits which, starting from row addresses, generate pre-decoding signals and a plurality of final decoding circuits which, starting from the pre-decoding signals, drive the individual rows of the array of the memory device. Each pre-decoding circuit has a push-pull output circuit with a pull-up transistor and a pull-down transistor and four parallel paths for the signal, a first path, supplied with low voltage, which drives the pull-up transistor during reading; a second path, supplied with a positive high voltage, which drives the pull-up transistor during programming and erasing; a third path, supplied with a low voltage, which drives the pull-down transistor during reading and programming; and a fourth path, supplied with a negative high voltage, which drives the pull-down transistor during erasing. Two selection stages enable selectively one of the first and second path, and one of the third and fourth path, depending on the operative step.

Abstract: An electronic regulator for driving a power device connected to an output load having a first portion and a second protection portion, the first portion including a controlled switching element connected upstream of the power device and controlled by a timer adapted to be operated in a short circuit or overload situation of the device, such that the load current can flow in the power device in a pulsed state clocked by the timer.

Abstract: A band-gap regulator circuit produces a voltage reference having a temperature compensation for second order effects. The regulator circuit includes: a Brokaw cell for producing a first band-gap voltage reference Vbg; a circuit portion including a comparator connected to the Brokaw cell output for providing a compensation voltage value Vcorr; and a summing circuit that sums together the compensation voltage value Vcorr and the first band-gap voltage reference Vbg.

Abstract: A voltage regulator circuit produces a voltage reference with high line rejection even for low values of the supply voltage. The regulator is of the type that produces a regulated voltage value for a bandgap voltage generator and includes a regulation circuit portion and a reference circuit portion. The regulation circuit portions is supplied with the supply voltage and has an output at which the regulated voltage value is produced and an input that receives a voltage reference. The reference circuit portion produces the voltage reference and includes a first circuit leg that receives the supply voltage through a controlled switch and a second circuit leg that receives the regulated voltage value.