Abstract: A device comprises a variable-gain input amplifier, a low-pass analog filter, a transversal continuous-time analog filter, and two distinct and parallel sampling channels interposed between the transversal analog filter and an RLL-NRZ decoder. The two sampling channels each comprise an analog-to-digital converter and a Viterbi detector arranged in series and operating according to sampling sequences that alternate with one another.

Abstract: The present invention concerns an electrically programmable and erasable non-volatile memory cell having a traditional structure but being inverted in the conductivity type of the component elements and lacking the second source diffusion.

Abstract: An electronic device smoothes a charge current peak in RLC output stages of switching step-up regulators, which stages include an input terminal and an output terminal with an inductance and a parasitic resistance in series therebetween, the latter corresponding to the series parasitic resistance of the inductance, and a capacitor connected between the output terminal and a ground. The device comprises a parallel of a resistor and a controlled switch connected between the inductance and the output terminal of the stage upstream of the capacitor. Advantageously, the switch would only be open during the charge transient of the capacitor.

Abstract: A process of manufacturing cross-point matrix memory devices which have floating gate memory cells having the source channel self-aligned to the bit line and the field oxide is disclosed. The process includes the steps of growing a thin layer of tunnel oxide on the matrix region; depositing a stack structure comprising a first conductive layer, an intermediate dielectric layer, and a second conductive layer; photolithographing with a Poly1 mask to define a plurality of parallel floating gate regions in the stack structure; self-aligned etching of the stack structure, above the active areas, to define continuous bit lines; and implanting, to confer predetermined conductivity on the active areas. Advantageously, the self-aligned cascade etching step for removing parallel strips from multiple layers, down to the active areas of the substrate, is discontinued before the field oxide is removed, and the implantation step is carried out in the presence of field oxide over the source active areas.

Abstract: A sense amplifier circuit for reading and verifying the contents of non-volatile memory cells in a semiconductor integrated device including a memory matrix of electrically programmable and erasable cells. The circuit includes a sense amplifier which has a first input connected to a reference load column incorporating a reference cell, and a second input connected to a second matrix load column incorporating a cell of the memory matrix. The circuit also includes a small matrix of reference cells connected, in parallel with one another, in the reference load column. Also provided is a double current mirror having a first mirror column which is connected to a node in the reference load column connected to the first input, and a second mirror column coupled to the second matrix load column to locally replicate, on the second mirror column, the electric potential at the node during a load equalizing step.

Abstract: An integrated semiconductor device comprises, reciprocally superimposed, a thermally insulating region; a thermal conduction region of a high thermal conductivity material; a passivation oxide layer; and a gas sensitive element. The thermal conduction region defines a preferential path towards the gas sensitive element for the heat generated by the heater element, thereby the heat dispersed towards the substrate is negligible during the operation of the device.

Abstract: A circuit for the generation of an electrical signal of constant duration comprises a capacitor, a constant current generator for charging the capacitor, and a voltage comparator to compare the voltage present at the terminals of the capacitor with a reference voltage. The voltage comparator supplies at an output a digital signal dependent upon the voltage across the capacitor. The constant current generator comprises a transistor biased with a voltage between gate and source obtained as the difference between the sum of two gate-source voltages of two transistors and a gate-source voltage of another transistor.

Abstract: This invention relates to an asymmetrical delay network connected between first and second voltage references and having an input terminal for receiving a trigger signal, and an output terminal. The network is of the type which includes at least one charge control transistor and at least one delay capacitor, connected in series with each other between the first and second voltage references. In particular, the charge control transistor has a control terminal connected to a generator of a constant current, and the output terminal delivers a delay signal which is synchronized to a first edge of the trigger signal. The invention also concerns a constant pulse generator including at least a first and a second of such asymmetrical delay networks.