Abstract: A method and implementing computer system is provided in which a service provider application for a network enables clients to selectively create communication channels and resources within the network. The application is programmed to monitor and examine the created resources for client activation and use of the resources. If no activity or use of the created resource occurs within predetermined client designated time periods, the client is notified and given an opportunity to keep or delete the resource. When the client wishes to delete the resource, or after a predetermined number of notifications to the client without a client response, the resource is deleted.

Abstract: Primary and secondary servers are coupled together for furnishing a backed-up video streaming function for outputting a series of video content presentations to a user group. The primary server functions as the primary provider of the video files and the secondary server is arranged to operate as a “hot stand-by” to back-up the primary server. In the event the primary server is disabled, the secondary server takes over for the primary server in furnishing video content in accordance with a common playlist. When the secondary server goes down for any reason, the illustrated methodology effectively re-synchronizes the video content and the video stream of the secondary server with that of the primary server such that the secondary server is enabled to resume the back-up function without interruption of the video file streaming process being carried on by the primary server.

Abstract: A method and implementing computer system is provided in which PCI bus load conditions are detected and dummy loads are selectively switched into the PCI bus under light load conditions in order to avoid voltage overshoot problems. Load control logic receives input signals representative of the presence or absence of adapters connected into PCI slots. The load control logic is connected to load control switches. The load control switches are arranged to selectively connect to the PCI slot or to a dummy load. The load control system is selectively operable, by controlling the load switches, to connect dummy loads into empty PCI slots to dampen the bus when light load conditions are detected to exist on the PCI bus. In a PCI system hot plug environment, the system is operable to quiesce the slot being hot plugged so that the adapter can be removed or inserted into a PCI slot while maintaining acceptable PCI bus loading conditions.

Abstract: A method and apparatus is provided for implementing a cache control system effective to eliminate many of the timing problems occurring in dynamic, high bandwidth cache control systems. In one exemplary embodiment, a dummy content addressable memory (CAM) cell is provided and is strategically placed on the chip layout farthest away from the cache word line driver circuit. The dummy output signal is a required input to a cache hit evaluation circuit such that premature cache hit outputs are eliminated. The dummy cell is designed to quickly discharge a cache match line and indicate a non-hit status when any address bit line produces a mismatch indication, especially for expanded bandwidth and dynamic systems where the address lines are more extensive and the system is synchronized to predetermined clock cycles. The cache system further operates in a prefetch mode to determine hits for next in-line requested addresses.

Abstract: A method and apparatus is provided for enabling the transformation of a domino circuit to a static circuit without requiring the re-design of the chip or integrated circuit mask set. The domino circuit masks may be designed to include additional unconnected devices as appropriate which may be added or connected into the circuit after chip design release by changing only interconnection masks. Spare devices can be added and selectively used to make a domino circuit metal-mask programmable into a logically equivalent static circuit. In a first exemplary method, extra devices are added to, and/or existing devices are re-wired in the domino circuitry to make a complementary equivalent static gate. In a second exemplary methodology, the domino circuit is converted into a pseudo-NMOS circuit using devices already available in the circuit and modifying the circuit connections thereto.

Abstract: A method and implementing system is provided in which light beams are projected from a first object upon a second object, and the relationship of the images projected upon the second object is used to provide an indication of the distance between the two objects. In an example, two light beams are projected at a predetermined angle of convergence from a vehicle such that the beams intersect between the vehicle and an object located in the path in which the vehicle is moving, for example, behind the vehicle. The intersection of the beams is selectively adjustable by adjusting the angle of convergence of the projected beams to provide an indication when the vehicle has backed to a position which has been determined to be a safe distance from the object.

Abstract: A data transfer flow control system includes a plurality of nodes or switches in a network, which are interconnected by transmission links. Resource management cells are transmitted along with data cells in information transfer sessions. As the amount of session traffic at any node increases, the level of occupancy of the buffers for that node correspondingly increases to temporarily store overflow data. At every network node, a “fair share” cell rate is determined for each output transmission link. Whenever the current cell rate (CCR) of any session exceeds the fair share cell rate for the output link at a node, the buffer occupancy threshold values for setting congestion indication fields in the resource management cells are adjusted downwardly such that a lower threshold buffer occupancy will effect a traffic congestion setting for that session.

Abstract: A method and implementing computer system enclosure is provided which includes a selectively removable base support unit which is designed to stabilize vertical mounting capabilities when the base unit is attached to the enclosure and to allow horizontal mounting of the electronics enclosure when the base unit is detached. The electronics enclosure includes a locking edge on one of its sides. The locking edge is selectively engageable with a base support unit to provide a wide footprint for stable mounting of the electronics enclosure on the side of the enclosure which has the base unit attached. In an exemplary embodiment, the locking edge is tapered to force a tight fit between the enclosure and the support base unit. A locking mechanism is also operable at one end of the support base unit-electronics enclosure interface to provide a positive stop to lock the enclosure in place relative to the support base unit.

Abstract: A method and implementing computer system is provided in which PCI bus load conditions are detected and dummy loads are selectively switched into the PCI bus under light load conditions in order to avoid voltage overshoot problems. Load control logic receives input signals representative of the presence or absence of adapters connected into PCI slots. The load control logic is connected to load control switches. The load control switches are arranged to selectively connect to the PCI slot or to a dummy load. The load control system is selectively operable, by controlling the load switches, to connect dummy loads into empty PCI slots to dampen the bus when light load conditions are detected to exist on the PCI bus. In a PCI system hot plug environment, the system is operable to quiesce the slot being hot plugged so that the adapter can be removed or inserted into a PCI slot while maintaining acceptable PCI bus loading conditions.

Abstract: A method and apparatus is provided for changing a self-timed circuit into a self-resetting circuit to reduce the inherent delay of the self-timed circuit by an amount of latency between the assertion of the data and the assertion of the valid signal. Circuitry is provided to enable the effective de-coupling of the self-timing operation to enable data to move through the logic circuitry without the latency associated with the reception and generation of "valid" and "complete" signals being necessary. On the "receiving" side (the circuit being set into self-resetting mode), the logic circuit does not have to wait for the reception of the "valid" signals to begin operation. On the "driving" side (the circuit sending the data), the logic circuit does not have to wait for the "completion" signal to arrive to permit a new operation to occur.

Abstract: A method and apparatus are provided in which a control scheme is implemented to enable a PCI bus to operate more than two PCI slots into which PCI devices may be installed. The PCI slots are checked to determine if a PCI device is installed in the slots and the speed at which the installed PCI devices are capable of running. If any of the slots has a 33 MHz device installed in any of the slots, the system is enabled to run more than two slots, and all of the PCI devices will run at 33 MHz. When no 33 MHz cards or devices are installed in the PCI slots, and PCI devices are only installed in the first two slots, then the system is enabled to run only the first two slots at the speed of 66 MHz. In one alternative embodiment, a default configuration routine sets the PCI bus speed at one of the operating frequencies and modifies that default if it is determined during a system configuration cycle that another speed is more appropriate.

Abstract: A method and apparatus is provided for implementing a cache control system effective to eliminate many of the timing problems occurring in dynamic, high bandwidth cache control systems. In one exemplary embodiment, a dummy content addressable memory (CAM) cell is provided and is strategically placed on the chip layout farthest away from the cache word line driver circuit. The dummy output signal is a required input to a cache hit evaluation circuit such that premature cache hit outputs are eliminated. The dummy cell is designed to quickly discharge a cache match line and indicate a non-hit status when any address bit line produces a mismatch indication, especially for expanded bandwidth and dynamic systems where the address lines are more extensive and the system is synchronized to predetermined clock cycles. The cache system further operates in a prefetch mode to determine hits for next in-line requested addresses.

Abstract: A process and implementing computer system for graphics applications in which information files such as texture maps (TMs) are prioritized and stored in a relatively fast local memory. The method of prioritization includes initially sorting the information files by order of the frequency with which corresponding graphics primitive elements are called by the application. The priority is adjusted such that the smaller TMs get an increase in their priority so that more TMs may be placed in faster graphics memory. Thereafter among similarly prioritized groups of information files, the larger of the files are first stored in the fast local memory and the remaining files are marked for storage in the system memory after the fast local memory has been fully utilized.

Abstract: A method and implementing computer system is provided in which PCI CONFIG.sub.-- ADDRESS and CONFIG.sub.-- DATA conventions are maintained in a large computer system and each PCI Host Bridge (PHB) CONFIG.sub.-- ADDRESS register and each PHB CONFIG.sub.-- DATA register have separate and system-unique addresses. In one example, the operating system provides a service to translate the device driver's configuration operation to a particular bus and device in the system, to a particular CONFIG.sub.-- ADDRESS or CONFIG.sub.-- DATA register of the PHB which has that device under it. By using this method, the hierarchical system can use architecture-independent routing of addresses down to the PHB that contains the appropriate CONFIG.sub.-- ADDRESS and CONFIG.sub.-- DATA registers.

Abstract: A method and apparatus is provided for enhanced error correction processing through a retry mechanism. When an L1 cache instruction line error is detected, either by a parity error detection process or by an ECC (error correcting code) or other process, the disclosed methodology will schedule an automatic retry of the event that caused the line error without re-booting the entire system. Thereafter, if the error remains present after a predetermined number of retries to load the requested data from L1 cache, then a second level of corrective action is undertaken. The second level corrective action includes accessing an alternate memory location, such as the L2 cache for example. If the state of the requested cache line is exclusive or shared, then an artificial L1 miss is generated for use in enabling an L2 access for the requested cache line.

Abstract: A method and apparatus is provided in which a site selection program is operable to selectively initiate sample testing of data transfer speed of a plurality of sites containing a predetermined data file. The methodology calculates a priority ordering of the plurality sites based upon the sample testing of data transfer speed, and divides the data file into portions for parallel access and delivery of the requested data file such that all of the portions are delivered to the user at approximately the same time, whereby faster channels will be requested to access and deliver larger file portions and relatively slower channels will be assigned to access and deliver relatively smaller portions of the requested data file. Upon receipt of the portions, the requested data file is assembled for further processing by the user.

Abstract: A methodology and implementing system are provided in which PCI system configuration data is made available to a host X86 system CPU through an intermediate PowerPC system. A bus converter circuit connected between the X86 bus and the PowerPC bus is effective to translate configuration addresses between the X86 and the PowerPC system. A PCI host bridge arrangement includes a primary PCI host bridge circuit and a plurality of secondary peer PCI host bridge circuits. The primary host bridge circuit is effective to process configuration data requests from the bus converter circuit which are directed to any of the secondary PCI host bridge circuits.

Abstract: A method 201 and implementing system 101 are provided in which information processing system resources are monitored for variant conditions which may exceed acceptable tolerances. A continued count of failed readings is maintained 207 and only when the number of failed condition readings exceed a predetermined failure repetition constant 209, is the operating system notified to take appropriate action. When a resource previously identified as a failing resource, subsequently yields "good" readings 303, a resource identifier is moved from a "failing" status to an "intermittent failure" status 309. Thereafter, when successive "good" readings exceed a predetermined success repetition constant 319, the resource is removed from the "intermittent" status 321 and the monitoring process 201 is continued.

Abstract: A method and implementing system is provided in which a gas, such as oxygen, is injected on to area of a circuit board to which an electronic component is being mounted. The injected gas causes a formation of a coating or surface alloy layer such as tin-oxide, on the solder joint. The coating causes the solder bead or joint to have a higher surface tension and a higher reflow temperature. In an exemplary double-sided double-pass assembly operation, circuit boards pass through a soldering oven on a first pass to attach components to a first side, and then the board is inverted and passed through the oven on a second pass while components are mounted on the opposite side of the board. During the second pass, a gas injection device is aimed at the component-to-board connection points on the inverted side of the board which were soldered on the first pass. The gas is injected at the point in the soldering reflow oven at which the temperature begins to exceed the solder reflow temperature.

Abstract: A method and implementing system are described in which planar board or motherboard stiffness is provided through a support structure mounted to the planar. The support structure includes support bars connected together to form a stiffening structure for the motherboard. The support bars are mounted within planes which are substantially perpendicular to the plane of the motherboard and in proximity to electrical connectors on the motherboard which are arranged to have circuit boards connected thereto. A board mounting apparatus is connected to the support structure to enable and guide the insertion and extraction of circuit boards to the motherboard with only enclosure side panel access. In one example, the circuit boards include guide pins which are inserted into slots of a mounting bracket, and the mounting bracket is selectively moved to exert an insertion or extraction force on a pin connector attached to the circuit board relative to a corresponding connector on a motherboard.