Abstract: A process and implementing computer system in which a graphics subsystem 117 having an XY coordinate addressing system interfaces with a host computer system having a linear addressing configuration. The subsystem includes an internal graphics engine 325, a host interface bus 301 and a host interface bus master circuit 321 for initiating data fetch and write requests to the host computer system memory 109. A subsystem host-XY circuit 327, 317 processes address requests between the subsystem and the host through the host system bus 105. A host system bus master circuit 315 is included in the subsystem 117 and is responsive to the host-XY circuit 327, 317 to access the host system bus 105 and effect the transfer of requested data through subsystem queuing units 303, 307 to the subsystem host interface bus 301 from which such requested data may be acquired by the requesting graphics engine 325.

Abstract: A method and implementing computer system is provided in which a network file system is operable to report multiple virtual files in various formats for a single native file in storage. When one of the files is opened, the file system reads data from the single native file and converts the format on the fly to the destination format that was opened by the operating system. The operating system thus converts files spontaneously on request and provides a synthetic file in a desired one of a plurality of possible formats while requiring the storage of only one native content file in server memory. Further aspects of the file system include provisions for additional features including Directory, Open File, Read File, Write File and Seek operations.

Abstract: A method and implementing system are provided which includes a PCI host bridge connected to a PCI bus. The PCI slots are applied to a switch array which is controlled by circuitry within the PCI host bridge in the example. The switch array is connected to interrupt control logic which is, in turn, coupled to the PCI host bridge. The methodology in one example uses the Interrupt Pin field in the PCI configuration space currently supported by the PCI Specification to identify an ISA interrupt signal line to which a migrated ISA device needs to be connected. Migrated ISA devices in PCI card connectors are then identified by determining the interrupt information associated with the ISA interrupt signal line identification method used. An interrupt switch array is then used to connect the migrated ISA device interrupt to the desired IRQx signal line and to the interrupt control logic. The switching array provides for a translation of PCI to ISA interrupts for connection to an interrupt controller.

Abstract: A process and system for transferring data including at least one slave device connected to at least one master device through an arbiter device. The master and slave devices are connected by a single address bus, a write data bus and a read data bus. The arbiter device receives requests for data transfers from the master devices and selectively transmits the requests to the slave devices. The master devices and the slave devices are further connected by a plurality of transfer qualifier signals which may specify predetermined characteristics of the requested data transfers. Control signals are also communicated between the arbiter device and the slave devices to allow appropriate slave devices to latch addresses of requested second transfers during the pendency of current or primary data transfers so as to obviate an address transfer latency typically required for the second transfer.

Abstract: A method and implementing system is provided which includes a switching device as part of a circuit board transmission line or trace serially connecting a plurality of device terminal sockets to a common node. When device terminals are left unconnected, corresponding segments of the connecting transmission line on the circuit board are disconnected to provide transmission line segments corresponding to the number of devices actually used. As a result, signal transition time for signals at the common node is optimized in accordance with the number of devices actually used.

Abstract: A method is provided for automatically enhancing verification of a design under test by using model checking on the state transitions captured during simulation. The enhanced verification is due to the fact that even though to all of the individual transitions captured were exercised during simulation, not all possible sequences of those transitions were necessarily exercised during the simulation, and the unexercised sequences may hide "bugs". The non-deterministic and exhaustive nature of the model checker ensures that all possible sequences comprising the captured state transitions are exercised. The methodology consists of utilizing the state transitions, and the inputs causing those state transitions as observed during simulation, to define legitimate input values that can be applied, nondeterministically and exhaustively, by the model checker to the design under test.

Abstract: A method and implementing computer system is provided in which a function or applet for example may be downloaded from a network server and graphical user interface (GUI) processor interprets a data stream consisting of GUI controls and attributes, and places the controls and attributes in a presentation space. In an exemplary embodiment, a web browser program loads an HTML (Hypertext Markup Language) from a GUI (Graphical User Interface) stream processor applet from a web server. The web browser then loads the GUI stream processor (GSP) from the web server and begins executing the GSP. The GSP then requests the GUI stream from the web server by opening a stream to a file, CGI (Common Gateway Interface) script or servlet on the server. The GSP then receives the GUI stream and assembles the user interface in the JAVA applet presentation space managed by the browser. The GSP may periodically update itself by repeating the last two steps.

Abstract: A method and implementing network computer system is provided in which completion point file positions of multimedia file presentations may be saved in persistent memory devices when a user desires to terminate a multimedia file being presented on a display device. In subsequent network and multimedia file accesses, a user is selectively able to begin play at the previously saved completion point in the multimedia file presentation, i.e. the file position at which the user had previously terminated play. The saved position in one example may include a refresh rewind of a predetermined length from the saved position to refresh a user with the content of the multimedia file being continued. In an exemplary embodiment, a user is also presented with a selection device by which the user may create a title for one or more saved files and corresponding completion points within each saved file. A default file designation may be automatically entered by the program.

Abstract: A method and apparatus is provided for securing trailer doors against tampering. In one exemplary embodiment, a locking device is mounted on the inside of a trailer door. The device includes a locking bolt which is selectively operated by a pneumatic valve in response to a signal selectively generated by an operator. In the example, the locking device is normally in a locked position and the locking bolt is effective to secure the trailer doors to the frame of the trailer. An operator selectively causes the generation of an "unlock" signal through the use of a wireless control device. The unlock signal, in turn, operates upon an electro-pneumatic valve device to effect an application of locally available high air pressure to a locking bolt actuator assembly. The air pressure is sufficiently high to effect the movement of a relatively heavy locking bolt out of a locking position, at which time the trailer doors may be opened for access to the trailer load.

Abstract: A method and apparatus is effective to preserve logic state potential levels in logic circuitry notwithstanding alpha particle collisions. Cross-coupled circuitry, including active devices, are implemented in a complementary logic circuit arrangement to hold current logic values in the event of a premature switching such as a switching that may be induced by alpha particle collision with the semiconductor logic circuit. Stabilizing transistor switching devices are arranged to sense an inappropriate or premature switching initiation and respond thereto by operating to maintain the appropriate logic levels within the logic circuitry. In one embodiment, the internal node of an upper circuit in a dual-rail logic circuit is connected to a gate terminal of a cross-coupled PFET device in the lower circuit.

Abstract: A circuit board guidance device is arranged to have a circuit board such as a PCI I/O board 205 inserted therein for connection into an electrical socket or connector 203 located on a system motherboard 201. The guidance device includes a guidance mechanism which translates an insertion force applied in one direction into a connecting force effective to move the circuit board in a second direction. The guidance device is effective to aid in locating the circuit board 205 above connector 203 on the system motherboard 201, and also to aid in forcing the desired electrical connection between corresponding connectors on the circuit board 205 and a system motherboard 201. The guidance device is also effective in aiding in the extraction of the circuit board from its connection to the motherboard connector 203. An I/O bracket 261 is implemented to provide EMI grounding to the system bulkhead.

Abstract: A method and apparatus is provided which allows overlapping of DMA line read and line write cycles. In an exemplary embodiment, the PLB Line Read Word Address bus is used with a DMA controller sideband signal to detect the conditions required to allow the DMA controller to start the line write one cycle prior to the completion of the line read cycle. A reference bit is set when the first word of a multi-word line transfer has been read. A sideband timing signal is generated one cycle prior to the completion of the read cycle indicating that there is only one read data phase remaining of the line read. If the first word to be written out to memory has been read or is available when the timing signal is generated, the write operation is begun prior to the final phase of the memory read transfer, and the read and write operations are overlapped thereby accomplishing an overlapped read/write transfer in fewer cycles than the sum of read and write transfer cycles if done sequentially.

Abstract: A method and implementing apparatus is provided for transferring data from a first device to a second device through a system coupling call. The coupling methodology is implemented to effect a direct coupling between a data producing device and a data receiving device such that data transfers between devices is passed more directly between devices with only minimal copying of the data during the transfer process. The coupling subsystem enables the construction of coupling modules which provide services and afford the opportunity to optimize the transference of data between two devices and permit the dynamic construction of coupling modules to provide coupling service between any pair of devices. In one example, video calls have been created to interface within the new data coupling environment.

Abstract: A system and method for increasing the gain per stage and signal edge transition speed, as well as the edge phase accuracy of an input signal. In an exemplary embodiment, a distributed clock signal is produced by an enhanced clock buffer circuit which includes additional weighted static gain chains connected within the buffer circuit. The buffer circuit retains the benefits of the split-drive, dual output transistor configuration, and also substantially improves circuit gain per delay gate by connecting the weighted static gain chains between pulse generators and output transistors of the buffer circuit. The gain chains are designed to rapidly propagate the edge that fires their respective output transistors but slowly propagate the edge that turns the output transistor off, by reducing the devices that propagate the shut-off transition. N-type and p-type devices within the buffer circuit are arranged and sized to promote the gain characteristic of the split drive buffer circuit.

Abstract: A method and implementing apparatus is provided for transferring data from memory to a file decoder which is effective to decode the file for further processing. In an illustrated example, a video file is decoded for presentation on a display device. The methodology includes enabling a plurality of control functions for access by a user or a user system in controlling the identity, sequence and flow of file transfers in order to optimize transfer efficiency in a data transfer transaction. Application programming interface (API) calls are provided by which playlists are constructed for transfer to the decoder. Further API calls are provided to enable pause and seek functions to be activated during a file transfer. A registration methodology is also provided by which predetermined processing events may be selected and recorded as they occur.

Abstract: A method and implementing computer system is provided in which an internet or web network user may invoke a hyperlink or site link listing mode to retrieve only the hyperlinks available on selected target pages rather than retrieving the entire text and graphics of the target pages. The network assembles only the available hyperlinks and associated activation code segments for presentation to the user. The user may then select from the presented hyperlinks, the most appropriate hyperlink or path in pursuit of the user's particular search goals. The hyperlink access methodology enables faster navigation through selected and more direct paths to particular search goals by selectively assembling and displaying listings of only hyperlinks of designated target pages rather than entire page presentations.

Abstract: A method and implementing system are provided in which the download program is designed to execute either from a command line in a main menu or from a diagnostics or service menu 201 as a service aid. The drive program 203 loads an executable file 205 which first reads from a drive specific data ("DSDATA") file 207. This allows the executable file 205 to configure itself to correctly perform micro-code download on a specific and designated drive device. The executable file program then proceeds to download the data contained in the drive binary firmware file 208 to a designated drive write buffer 209. The program then prompts the operator for final confirmation that the drive should be updated. Once the operator confirms the download, the executable file program issues the command to load the firmware into the drive.

Abstract: A method and implementing system 101, are provided in which a computer system is arranged for connection 210 to a network system such as the Internet. A user of the computer system may selectively display 401 a listing of network data path and site history files from previous network sessions, and select one or more items from the list for modification 407, 409, 411. The user may then modify the current history file by creating 411, 701 a new current history file. A new current history file may also be modified by exchanging 407, 501 or appending 409, 601 the selected and modified selected items with the current history file to create a new current history file. The newly created history file then includes data paths and/or portions thereof, which were successfully used in previous network sessions.

Abstract: A process and implementing computer system in which an arbitration circuit is comprised of a plurality of state machines 301, 303 and 305 which combine to receive various system timing signals and provide a data bus grant signal effective to enable data streaming of sequential data blocks of information from an L2 cache memory 109 without intervening wait states between the data blocks.

Abstract: A method and apparatus is provided in which a data file acquisition program is operable to determine the data transfer speed of a plurality of devices containing a predetermined data file. The methodology calculates a priority ordering of the devices based upon the data transfer speed, and divides the data file request into portions for parallel access and delivery of the requested data file such that all of the portions are delivered to the user at approximately the same time whereby faster devices will be requested to access and deliver larger file portions and relatively slower devices will be assigned to access and deliver relatively smaller portions of the requested data file. Upon receipt of the portions, the requested data file is assembled for further processing by the user.