Abstract: A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for rendering the graphics primitives. A graphics processor which includes an arbitration logic device enables the graphics processor to temporarily arbitrate shared resources to dissimilar graphics drawing engines. The arbitration logic allows data from the dissimilar drawing engines to be prioritized, depending on the configuration of the underlying computer system, for accessing shared resources.

Abstract: A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes a XY address for rendering the graphics primitives. A graphics processor which includes a command address feed logic device decodes the display list to determine the register locations in a register file to fill with data. The command address feed logic device decodes the display list and orders a group of registers in the register file in order to perform a sequential write to the register file. By sequentially ordering the register file locations, the command address feed logic device is able to write null or zero data values to the register locations which are not needed to render a primitive, while maintaining a single write cycle to the register file.

Abstract: A method and implementing computer system is provided including a multimedia server connected in a network configuration with client computer systems. The multimedia server includes various functional units which are selectively operable for delivering and effecting the presentation of multimedia files to the client such that a plurality of multimedia files are seamlessly concatenated on the fly to enable a continuous and uninterrupted presentation to the client. In one example, client selected video files are seamlessly joined together at the server just prior to file delivery from the server. The methodology includes the analog to digital encoding of multimedia segments followed by a commonization processing to ensure that all of the multimedia segments have common operating characteristics.

Abstract: A method and implementing system are provided for determining and retaining an identification number relevant to an electronic system component and/or component configuration. In an exemplary embodiment, existing pull-up resistors within a computer system are connected in a manner to enable associated circuitry to determine a pre-assigned identification number for the computer system. The identification number is stored in an identification number register and accessible for providing the identification number in response to a requests from other devices within the system.

Abstract: A method and apparatus is provided for implementing a memory cell array having a performance-improved critical read path using a boost amplifier configuration. The memory bit line is broken into small segments with a boost amplifier and the bit line is connected to the input of the amplifier. The output of the amplifier drives the global bit line. The amplifier is turned "on" during a "read" and turned "off" during a "write". During a read, one memory cell within one array segment is turned on. The memory cell drives the differential signal on to the local bit line pair. Also during a read, the boost amplifier which attaches to that local bit line is enabled. The boost amplifier amplifies the input signal (local bit line pair) and drives that signal on to the global bit line. Since the bit line is broken into small segments with boost amplifiers, there are many boost amplifiers attached on the global bit line.

Abstract: A methodology and implementing system 101 are provided in which a PCI bus is enhanced to operate at a plurality of data transfer speeds, including for example, 133 MHz in order to accommodate subsystem boards operating at higher frequencies, while at the same time allowing normal 66 MHz PCI clocking for devices designed to operate at the lower 66 MHz standard PCI speed. Master strobe MSTB 303, 403 and target strobe TSTB signals 309, 411 are generated in a handshaking methodology to determine if a master data transaction requesting device and a target data transaction device are designed to operate at the higher data transfer frequency. Higher frequency capable devices or boards are run at the increased frequency when both the requesting master and the selected target devices request the higher transfer rate, and standard devices or boards are run at the lower standard PCI frequency, while both master and target devices are coupled to and run from the same multi-speed PCI bus 125.

Abstract: A method 401 and implementing system 101 are provided in which a site selection program is operable to selectively initiate sample data transfers from a plurality of mirror sites 313 on the Internet, and to make a determination, prior to a selection of a site to be contacted for a download, as to which of the sites exhibits the best transfer rates at the time of the site selection. The methodology includes a cut-off time 507 process for terminating a sample operation of any one site if the transfer time for a predetermined number of bytes "X" exceeds a predetermined maximum amount of time "Y" for the sample operation for any particular site. When the maximum time is exceeded, the program stores the number of bytes transferred during that time for comparison with other site data. After all sites have been sampled, the program determines a selected site which exhibits the best rate of data transfer, and selectively initiates the establishment of a communication link with the selected site.

Abstract: A graphics system includes a graphics processor for rendering graphics primitives with a list of display parameters. A host processor generates a display list which includes an XY address for rendering the graphics primitives. A graphics processor, which includes a bypass logic circuit, enables the graphics processor to temporarily store display list commands in an internal storage device while previously fetched display list data is being processed. The bypass logic circuit allows the graphics processor to bypass the internal storage device and write fetched command directly to an execution unit in the graphics processor. By having the bypass capabilities, the graphics processor is able to optimize the internal storing of commands in the display list in the internal storage unit.

Abstract: A computer system includes a memory subsystem which has DIMM slots capable of receiving both DRAM and SDRAM memory module devices. A memory device detection methodology detects the presence of installed memory modules in the memory module slots, and signal levels on predetermined pins of the installed memory modules are processed to identify the specific type of memory module installed. The mode of an associated memory controller is set according to the type of module detected to be present, and the characteristics for the memory module are read.

Abstract: A method and apparatus are provided which are implemented in a chip I/O buffer-multiplexor circuit or I/O buffer cell 201. The I/O buffer portion includes a receiver circuit 205 for receiving bus input signals to the buffered chip, and a driver circuit 203 for driving output signals from the buffered chip to a data bus. An integrated multiplexor or MUX circuit 207 selectively gates one of three possible signals to chip internal logic. The three signals applied to the MUX circuit include a boundary scan test signal BS MUX for testing scan points in an integrated circuit, a bypass Data In signal DI which is generated by chip internal drive logic, and a DQ signal received by the I/O buffer receiver circuit from a data bus. The data input node of the I/O buffer is wired directly to the new multiplexor data input. Additional control signals are provided for orthogonal selection of the three multiplexor data inputs.

Abstract: A process and implementing computer system for graphics applications in which polygon information is organized, stored and transferred in terms of "UV" addressable designated texel blocks of information within the graphics system. The texel information blocks are re-configured and remapped from normal graphics "UV" configuration to "XY" addressable configuration in order to allow storage of the texel blocks in otherwise unused sections of the relatively fast frame buffer memory.

Abstract: A process and implementing computer system in which a power-on self-test (POST) routine initially clears 203 a mask register 111 which is effective to mask or block data from being written to addresses in a synchronous DRAM or SDRAM 107. After disabling interrupts and caches, the tested SDRAM memory 107 is cleared to all "0"s. Sequential data byte lanes are tested by writing bits in a predetermined pattern to inject errors at predetermined bytes in SDRAM, setting selected mask register bits and then writing all "0"s to the predetermined addresses. The tested memory locations are read and compared with the predetermined pattern for errors. Detected errors are noted by recordation and the memory locations are cleared as the method recycles until all of the data byte lanes have been tested and the results recorded.

Abstract: A process and implementing computer system for graphics applications in which polygon information, including transparency, color and other polygon characteristics, is organized, stored and transferred in terms of areas or tiled blocks of information in a matrix configuration. The polygon bytes of texel information are organized in an exemplary 8.times.8 matrix row and column format in the graphics subsystem for improved cache-hit efficiency and translated to and from the linear addressing scheme of a host storage device when the host storage is accessed to refill the graphics cache. The bytes comprising the memory tiles of polygon information are arranged such that a complete tile of information is transferred in one burst-mode host memory access to minimize normal multi-line access arbitration and other typical access delays.

Abstract: A method and implementing system are provided in which specific byte requests made by a functional unit within a computer system effect the return of a word containing the requested byte to a register device within a CPU. The returned word is stored "as is" and without alignment, together with mask and alignment data indicative of the location of the requested byte within the stored word. Alignment relative to the requested byte is thereafter accomplished using the mask and alignment data just before use of the requested byte by the functional unit. The alignment function is thereby accomplished outside of the processor critical path which obviates the typical memory-processor mismatch delay inherent in prior art data alignment networks and substantially shortens the critical path in the memory access stage of the processor's pipeline.

Abstract: A process and implementing system is provided for conducting a memory test for isolating and identifying failed cache memory modules in a memory subsystem of a computer system. The methodology initially selects 303 a block of memory which is twice the size of the cache 105 being tested. The cache 105 is then disabled 305 and a first test is performed 307 on the selected block of to isolate byte addresses of individual bit failures. If bit failures are detected 308, the appropriate byte address is mapped 310 and the test is ended 321. If no bit errors are detected in the first test, the cache is enabled 309 and a second test is performed and the block is tested 311 for failures. Any detected failures are assumed to be cache failures and the appropriate byte address is mapped 315. The cache is again disabled 317. An appropriate message is then displayed 319 to indicate the results of the testing.

Abstract: A process and implementing computer system for graphics applications in which polygons from a frame buffer, which may have three dimensional depth, color and other characteristics, are compactly reassembled and drawn to a fast memory for high speed and highly efficient processing. Polygons are divided into shaped segments which correspond to the shapes of the polygons. Corresponding memory storage references to the polygon objects themselves enable optimal processing efficiency and speed.

Abstract: A process and implementing computer system for graphics applications in which polygons from a frame buffer, which may have three dimensional depth, color and other characteristics, are compactly reassembled and drawn to a fast memory for high speed and highly efficient processing. Polygons are divided into shaped segments which correspond to the shapes of the polygons. Corresponding memory storage references to the polygon objects themselves enable optimal processing efficiency and speed.

Abstract: A method and apparatus for printing lenticular pictures includes imposing lines of information in the form of segmented images of a scene onto a light sensitive material. Alternate segments or lines are provided from different perspective views of the same scene to be printed. The light sensitive material has a transparent lenticular material attached thereto. The light sensitive material is exposed, from the side opposite the lenticular material, by light from an illuminated image. The exposure may be effected by optical projection or by contact printing or by CRT image projection or other device. A reference grid, having a pitch slightly different from the pitch of the lenticular material, is positioned on the lenticular material and is effective to cause a Moire pattern to become visible when the lenticular material is moved relative to the light sensitive material.

Abstract: A CRT display system includes a CRT with a lenticular material placed upon the outward face of the CRT. The system further includes a sensing device in the field of view of the CRT and control circuitry connected between the sensing device and the CRT. The control circuitry is responsive to signals received from the sensing device to control the synchronization and formation of a composite of strips of visual input from four different perspective views of a scene to be presented on the CRT through the lenticular material such that a viewer perceives depth in the composite scene displayed on the CRT.

Abstract: A CD player, including an improved controller circuit, is capable of displaying a plurality of photo quality images together with audio snippets which correspond to the individual visual presentations on a series of sequential CDs. The controller circuit includes a detector circuit for detecting the presence and absense of an audio signal, providing an audio signal to the controller for appropriate processing. Timing signal generators operate to sequence CHANGE DISC, PLAY and STOP functions to achieve automatic and continuous photo CD presentations for a plulality of Photo CDs being played.