Abstract: A common-mode feedback circuit comprises a reference generator (12) for generating a signal corresponding to a desired common-mode operating point connected to a common-mode bias circuit (14) for generating a second signal corresponding to the common-mode operating point of the outputs (V.sub.out.sup.+, V.sub.out.sup.-) of the fully differential operational amplifier. In the preferred embodiment, the common-mode bias circuit (14) includes a sensing circuit (58) comprising two MOS transistors (60, 62) having sources and drains connected together. The MOS transistors (60, 62) operate in the ohmic region to provide a variable load responsive to the output signals (V.sub.out.sup.+, V.sub.out.sup.-) connected to their gates.

Abstract: Disclosed is an integrated circuit process which includes forming two types of active devices: a first set of IGFETs has silicide gates, and the second set has TiN gates. The same TiN thin film layer also provides local interconnect. Optionally the TiN-gate devices may be used for high-voltage devices and the silicide-gate devices used for logic devices. The TiN gates in the second set of transistors and the TiN interconnect are formed by providing a thin film insulator pattern, depositing a titanium layer overall, heating the titanium in a nitrogen bearing atmosphere, and subsequently etching the titanium nitride obtained.

Abstract: A bit line latch sense amp is disclosed which substantially eliminates a number of problems associated with prior art sensing schemes which result through asymmetrical operation proximately caused by the use of separate bit line and separate sense amplifier pre-charge circuitry. The invention disclosed herein precharges the sense amplifier and its associated bit line at substantially the same time and does not require separate precharge circuitry for doing so.

Abstract: An electron image projector (10) is exposed to a heat source (22) to induce the emission of electrons (20) which flow from a pattern (14) of a mask (12) to a photoresist layer (18) of a substrate (16). An electron field (26) is applied across the substrate (16) and the mask (12) to accelerate the electrons (20) from the pattern (14) to the photoresist layer (18) to form a shape (24) on the photoresist layer (18) which reproduces the shape of the pattern (14). A projection system (28) can be disposed between the substrate (16) and the mask (12) to selectively direct the plurality of electrons (20) from the pattern (14) to the photoresist layer (18).

Abstract: A CCD imager array is formed at a face (30) of a semiconductor layer (12) and comprises a plurality of CCD cells (34) formed in rows and columns. A plurality of continuous buried gates (27) are each disposed between adjacent columns of the cells (34), and each buried gate (27) extends from the face (30) into the semiconductor layer (12). Each buried gate (27) includes a gate conductor (24) and a gate insulator (26). The buried gates (27) define for each cell (34) a charge collection region (66). A bias voltage source is operable to selectively apply a bias voltage (60) to the buried gate conductors (24), thereby creating a depletion region (64) that substantially includes the charge collection region (66). CCD clock gates (32) are operated independently of the buried gates (27) to read out the charge collected during an integration phase (58). The array of the invention is particularly useful in recording X-ray and near infrared electromagnetic radiation.

Abstract: An EEPROM cell and array of cells is disclosed having buried diffusion source/drain lines and buried diffusion erase lines. The cells further include coupling between the floating gate and control gate above the source/drain diffusion. The disclosed cell allows high packing density and operation at low voltages.

Abstract: A baseboard for orthogonal mounting of integrated circuit chips is described. Plural channels (14) are anisotropically etched in a silicon baseboard (10). A corresponding plurality of integrated circuit chips (12) are inserted into the channels (14). A number of baseboard contact pads (18) are formed adjacent each channel (14), and are solder bonded to corresponding chip conductor pads (16). Interconnect conductors (20, 28) provide connection of each baseboard pad (18) either to other chips (12) or to connector pads (22) located adjacent an edge (26) of the baseboard chip mount (10). A coating (30) of silicon carbide over the surface of the baseboard chip mount (10) improves the thermal efficiency of the assembly.

Abstract: The present invention provides a method for inhibiting the oxidation of a titanium layer during the direct reaction of the titanium with exposed silicon areas of an integrated circuit. In one embodiment of the present invention, a titanium nitride layer is formed on the surface of the titanium layer in the reactor where the titanium layer is deposited. The titanium nitride layer provides an effective barrier against oxidation. Thus, the formation of titanium dioxide is inhibited. In addition, in those areas where titanium nitride local interconnect is to be formed between diffused areas, the extra thickness provided by the top titanium nitride layer adds in the integrity of the conductive layers. By conducting the silicidation in a nitride atmosphere, diffusion of the nitride from the titanium nitride layer into the titanium layer and substitution of those lost nitrogen atoms by the atmosphere occurs thus providing a blocking layer for the formation of titanium silicide shorts.

Abstract: A column select circuit for a memory device is disclosed which, for unselected data lines, provides a high impedance output. Each data line, and a corresponding decoded address signal, is received by a gate which passes the logic state of the data line (inverted), if selected, to a driver. The decoded address signal is also communicated to the driver, for tri-stating the driver for unselected data lines. The driver consists of a p-channel pull-up and an n-channel pull-down, with an n-channel isolation transistor connected in series therebetween. The driver output is at the junction of the pull-up and isolation devices. The gates of the pull-up and pull-down transistors are connected to the output of the gate, with the gate providing a high logic level when not selected, turning off the pull-up device.

Abstract: The present invention is described in conjunction with the fabrication of a dRAM cell which an important application of the present invention. The described cell provides a one-transistor/one-capacitor dRAM cell structure and array in which the cell transistor is formed on the sidewalls of a substrate trench containing the cell capacitor; the word and bit lines cross over this trench. This stacking of the transistor on top of the capacitor yields a cell with minimal area on the substrate and solves a problem of dense packing of cells. One capacitor plate and the transistor channel and source region are formed in the bulk sidewall of the trench and the transistor gate and the other plate of the capacitor are both formed in polysilicon in the trench but separated from each other by an oxide layer inside the trench. The signal charge is stored on the polysilicon capacitor plate by an electrical connection of the source region with the polysilicon capacitor plate.

Abstract: The rate of single event upset in a memory cell is reduced by a pair of active devices in the cross-coupling between a pair of inverters. The active devices are controlled by voltages internal to the memory cell such that writing into the cell is not slowed significantly.

Abstract: Single event upset hardening is provided in a static random access memory cell, including cross-coupled inverters, by the restoration of voltages at selected nodes within the cell by a pair of transistors connected to the cross-coupling between inverters.

Abstract: EEPROM memories with crosspoint cells using buried source and drain lines plus merged floating gate transistors with floating gate coupling to control gate over the buried line insulator for high packing plus low voltage operation.

Abstract: The described embodiment of the present invention provides a memory cell which is fabricated using a self-isolating structure and provides misalignment tolerance in the design of the cell thereby eliminating the need for additional area to be reserved for isolation structures and misalignment tolerances.

Abstract: P channel and N channel CMOS FETs (22, 24) and a process for their simultaneous fabrication with a minimal number of masking steps are disclosed. After formation of gates (30, 32) for both P channel FETs (24) and N channel FETs (22), a first N type dopant implanting step forms lightly doped drain extensions in both the P channel FETs (24) and the N channel FETs (22). A mask then protects the N channel FET area (22) while a P type dopant is implanted in source and drain regions (36) of the P channel FET (24) at a greater concentration than the prior implanted N type dopant. Another N type dopant implant occurs to both the P channel FET (24) and N channel FET (22). The N type dopant dosage used in this second N type dopant implantation step is greater than the dosage used in the first N type dopant implantation step.

Abstract: A silicon-on-insulator MOS transistor is disclosed which has contact regions on both the source and drain sides of the gate electrode for potentially making contact to the body node from either side. Each contact region is of the same conductivity type as the body node, (for example, a p-type region for an n-channel transistor), and may be formed by blocking all source/drain implants from the contact regions, so that the contact region remains substantially with the same doping concentration as that of the body region. A mask is provided prior to silicidation so that the contact regions on either side of the gate electrode are not connected by silicide to the adjacent source/drain doped regions. Once a side is selected to be the source of the transistor, ohmic connection is then made between the abutting source region and the contact region by way of contacts through an overlying interlevel dielectric and metallization.

Abstract: A BiCMOS bandgap reference voltage circuit is disclosed wherein substantial independence from a specified variation in supply voltage is accomplished through establishing a feedback loop between the output of the circuit and the input of the circuit such that the input is a function of the output.

Abstract: A sealed gate FAMOS transistor (28) disposes a thermal oxide layer (40) about the floating gate (34) in order to isolate the floating gate (34) from the planar isolating regions (44) between floating gates (34). Trench isolating regions (54) are provided between control gates (50) to enhance programmability of the sealed gate FAMOS transistor (28).

Abstract: A threshold control BICMOS TTL input buffer is disclosed which substantially eliminates input trip point variation across power supply, process, and temperature and additionally minimizes buffer power dissipation.

Abstract: The present invention provides products and methods of forming an epitaxial silicon layer on an implanted buried insulator silicon on insulator structure (10). A silicon film (16) is pre-treated to remove residual oxide and surface damage layers, but in such a way as to not damage the silicon film (16) or insulating layer (14) below the silicon film (16). A layer of amorphous silicon (18) is formed on the silicon film (16) in processes to avoid formation of polycrystalline silicon, and also to avoid damage to the silicon film (16). The layer of amorphous silicon (18) is annealed to form an epitaxial layer of single crystalline silicon (20).