Abstract: A computing system has a wireless interface, for example an infrared interface. The infrared interface is used to directly transmit configuration information to and/or receive configuration from a configuration storage device without going through the standard I/O interfaces of the computing system. This is done by connecting the infrared interface directly to the configuration storage device. Alternately, the infrared interface is used to allow direct connection to a memory bus without using an I/O bus. This allows the computing system to send out diagnostic information without using the I/O bus. The infrared interface can be full duplex allowing requests for diagnostic information to be made by a handheld computing system such as a handheld computer or a calculator. The infrared interface may also be used to download data and programming code to a handheld computing system and for receiving data from the handheld computing system.

Abstract: A system and method is disclosed for a personal computer (PC) to auto-detect the configuration of mass storage devices installed by the user. At least one drive table contains numerous configurations pertaining to industry-standard mass storage devices. These numerous configurations are compared to the configuration which is auto-detected. If a match occurs, then the PC adopts that configuration. However, the PC permits the user to override this configuration by entering a custom configuration or by selecting another configuration from the drive table(s). If no match occurs, then the user is permitted to select one of numerous generic configurations pertaining to mass storage devices. Accordingly, the PC system configuration if used on a different PC will function properly if the selected generic configuration matches a configuration found in the BIOS program of the different PC.

Abstract: A computer system comprising a removable optical disk having active circuitry thereon and a disk player is disclosed. The optical disk includes a storage medium for storing data on one side and active circuitry for processing the data on the other side. The disk cartridge includes most of the high speed components of the computer system, while the disk player includes those components which are least likely to change over time. By combining the active circuitry with the data and programs to be processed thereby on a single disk cartridge, the problems associated with maintaining and configuring the system are substantially reduced compared to prior art systems.

Abstract: A computer software-related device and method uses regression testing techniques for testing computer hardware and/or software application(s). Input data and commands from a user are stored, and are sent to a hardware/software system under test. Signatures (representative of visual display data) which are received (with a selected prevalence) as a result of the sent input data and commands are also stored. On command of a user, the stored signatures, input data and commands are subsequently sent to the hardware/software system under test, and new signatures are generated. These new signatures are compared with the stored signatures, and the results of this comparison are used as an indication that the hardware/software system under test is performing as expected.

Abstract: The method uses statistical information obtained by running the computer code with test data to determine a new ordering for the code blocks. The new order places code blocks that are often executed after one another close to one another in the computer's memory. The method first generates chains of basic blocks, and then merges the chains. Finally, basic blocks that were not executed by the test data that was used to generate the statistical information are moved to a distant location to allow the blocks that were used to be more closely grouped together.

Abstract: A system and method for managing the reserved memory in a microcomputer copies selected portions of reserved memory to a new reserved memory having a faster access time, and allows any free portions of the new reserved memory to be accessed by a typical software application. After the selected portions of reserved memory are copied, all access to an address within a selected portion are re-directed to the new reserved memory. Any free portions of new reserved memory have additional, accessible memory re-mapped to these free portions.

Abstract: A method is provided for maintaining cache coherence in a multiprocessor computer system having a potential for duplication of data in a plurality of storage location, where there is cache associated with each processor by storing a processor address and a "hint" or for each cache. More specifically, where the multiprocessor computer system employs doubly-linked lists for identifying a previous master of sharable data and a next master of the sharable data, the method includes the steps of passing the current address of the current master from the current master to the previous master; passing the current address of the current master from the current master to the next master; passing the current index of the current master from the current master to the previous master (the current index being a collection of all information needed by the current master to find a coherence block); and passing the current index of the current master from the current master to the next master.

Abstract: A specific dye set, comprising Acid Yellow 23, Direct Red 227, and Acid Blue 9, yields true, vivid colors on specially coated paper and transparency, and yields true colors on uncoated or "plain" papers. This dye set, which is intended for 300 dpi thermal ink-jet printers, is a distinct improvement over a prior art dye set.

Abstract: A computer related system and method uses regression testing techniques for testing computer hardware and/or software application(s). Input data and commands from a user are stored on a host, and sent to an interface device, which then sends them to a hardware/software system under test. Visual display data on a visual display device is thereby affected. Signatures (representative of the visual display data) are generated by the interface device as a result of input data and commands sent to the interface device and system under test. These signatures are received and stored by the host. On command of a user, the stored signatures, input data and commands are subsequently sent to the hardware/software system under test, and new signatures are generated. These new signatures are compared with the stored signatures, and the results of this comparison are used as an indication that the hardware/software system under test is performing as expected.

Abstract: A computing system includes a processor, a system memory containing data utilized by the processor and two cache memories. Each cache memory is connected directly to the processor. A first cache memory is connected to the processor. A second cache memory is connected to the processor and to the system memory. The second cache memory contains a subset of data in the system memory. The first cache memory contains a subset of data in the second cache memory. Data integrity in the system memory is maintained using the second cache memory only. During the execution of a first instruction data required for execution of the first instruction might not be available in the first cache memory. The data required for execution of the first instruction is obtained from the second cache memory and written into the first cache memory.

Abstract: A computing system includes a processor, a system memory containing data utilized by the processor and two cache memories. Each cache memory is connected directly to the processor. A first cache memory is connected to the processor and to the system memory. The first cache memory contains a subset of data in the system memory. A second cache memory is also connected to the processor. The second cache memory contains a subset of data in the first cache memory. Data integrity in the system memory is maintained using the first cache memory only. Whenever the processor writes data, the processor writes data both to the first cache memory and to the second cache memory. Whenever the processor reads data, the processor attempts to read data from the second cache memory. If there is a miss at the second cache memory, the processor attempts to read data from the first cache memory. If there is a miss at the first cache memory, the data is retrieved from the system memory and placed in the first cache memory.

Abstract: A computer hardware-related device and method is used for regression testing techniques involving the testing of computer hardware and/or software application(s). Input data is received from a host, and is directed to software application(s) on a System Under Test (SUT). Command are also received from the host, which causes the capture of a representation of visual display data from a visual display device on the SUT. A representation of this visual display data is then sent to the host. When a command and a representation of visual display data from the host (previously obtained from the SUT) is received, a new representation of visual display data is captured from the visual display device on the SUT. A comparison is than made between the new visual display data representation and the visual display data representation received from the host.

Abstract: A method for arbitrating access by a plurality of agents to a bus utilizes a priority access list. Each agent in the plurality of agents has a position on the priority access list. This position indicates the agent's relative priority level of access to the bus. When at least one agent from the plurality of agents requests access the bus, bus access is granted to the agent among the requesting agents which is highest on the priority access list. Once an agent from the plurality of agents has gained access to the bus, the agent which gained access to the bus is moved to the bottom of the priority access list.

Abstract: A method for efficient generation of complied code is presented. In order to gain significant performance advantage with a minimum of code expansion, out-of-line code sequences are used. An out-of-line code sequence is a series of instructions that are invoked by a simplified calling mechanism in which almost no state-saving is required. Additionally, out-of-line code sequences is designed so that a single copy can exist on a system and all processes running on that system can access it. A series of out-of-line code sequences can be generated, each member of the series being tailored to a particular combination of compile-time information.

Abstract: A system for testing a RAM array bus transaction buffer without halting system operation or using a special protocol, including a RAM control selection circuit for providing to the RAM either a set of normal control, data and address signals or diagnostic control, data and address signals; a Diagnostics Mode Bit Register (DMBR); a Diagnostics Address Register (DAR); and means for recognizing instructions to write to those registers or to a fictitious Diagnostics Data Register (DDR). First a normal write operation is executed to the DMBR, to control a RAM control selection circuit. The RAM control selection circuit chooses as RAM control signal sources a set of diagnostic sources rather than normal system sources. Second, a selected RAM address is written to the DAR. Third, a write operation is performed to the DDR, causing the selected data to be written to the RAM at the address specified by the DAR. Data is similarly read from the RAM through the DDR.

Abstract: Error detection or correction is provided on the same chip as DRAM memory. Because data and error correction bits need not travel on an external bus, error detection/correction can be conducted on a larger number of bits than the width of the data bus. When using memories which provide for access to a row of memory, such as static-column or fast-page mode memories, error correction is conducted on an entire row of memory during one error correction cycle. Following operations of the correction cycle, the data within a row of memory can be accessed independently of the EC circuitry.

Abstract: A keyboard mounted, hand-operable input device for controlling the movement of a marker on a computer display is described and includes a tray which is elongated along a first axis, has right and left closed ends and is mounted for translational movement along its first axis. A hand-operable roller is rotatably mounted in the tray and is movable therewith. A rotary encoder is mounted on and movable with the tray and is maintained in engagement with the roller so that it provides signals indicative of the roller's rotary motion. A translational encoder is movable with the tray and provides signals indicative of translational movements of the tray. By directly coupling the roller to the rotary encoder and having both move with the tray, accurate rotary motion indications are thereby derived.

Abstract: A multi-way set-associative cache memory stores data in a plurality of random access memories. Data in the multi-way set-associative cache memory is organized in lines of data. The multi-way set-associative cache memory allows access of single words and allows access of multiple-words of a length specific to the multi-way set-associative cache memory. Within the plurality of random access memories, data are placed such that corresponding words of each line of data is placed in different random access memories. Further, each word from each multiple word is placed in different random access memories. For single word access, one word is accessed from one of the plurality of random access memories. For multiple-word access, one word from each of the plurality of random access memories is accessed.