Abstract: Explicit instructions are provided that enable software to directly control insertion of information into a translation lookaside buffer (TLB). A first pair of instructions enable information to be inserted into a data TLB and a second pair of instructions enable information to be inserted into an instruction TLB. In each of these pairs, the first instruction inserts the virtual address and the associated physical address. In response to the second instruction of each of these pairs, additional information about that physical page, such as protection information and flags, is inserted.

Abstract: A quick freeze method and a clean freeze method allow for the halting of operation of all computing sections within a computing system upon detection of an error. In the quick freeze method, a first computing section detecting an error immediately halts operation. The first computing section notifies all adjacent computing sections of the detection of the error. Each computing section in the computing system, upon receiving notification of the detection of the error, immediately halts operation and notifies all adjacent computing sections of the detection of the error. In the clean freeze method, when a first computing section detects an error, all computing sections are notified of the detection of the error. When all computing sections of the computing system have been notified, all the computing sections within the computing system halt operation simultaneously.

Abstract: A card guide for positioning a circuit card relative to a backplane is disclosed. The card guide provides electrical contacts to a ground plane on the circuit card in addition to positioning the card. The card guide utilizes two types of protuberances to reduce the force needed when the card is inserted or removed from the card guide, while providing accurate mating of paired connectors.

Abstract: A method and apparatus for tracking and identifying printed circuit assemblies is presented. Information about each printed circuit assembly (PCA), including the current revision level of the PCA is stored within a non-volatile random access memory (RAM) within each PCA. The stored information may be accessed by a user through a dedicated bus and hardware designed for this task. Additionally, through the dedicated bus and hardware, the user may update the information within the printed circuit assembly.

Abstract: A computer bus structure is provided which permits replacement of removable modules during operation of a computer wherein means are provided to precharge signal output lines to within a predetermined range prior to the usage of the signal output lines to carry signals, and further, wherein means are provided to minimize arcing to pins designed to carry the power and signals of a connector. In a specific embodiment, pin length, i.e., separation between male and female components of the connector, are subdivided into long pin length and short pin length. Ground connections and power connections for each voltage level are assigned to the long pin lengths. Signal connections and a second power connection for each voltage level is assigned to the short pin lengths.

Abstract: An improved integrated circuit chip design which is better adapted to testing using existing circuit testers is disclosed. The chip includes a parallel load instruction which reduces the number of words of tester memory needed to load the internal scan registers. The parallel load instruction loads memory cells connected to the input pins of the chip which are then shifted into the scan registers.

Abstract: A technique for rasterizing a line having a predetermined width and slope, including the step of providing stored data associated with predetermined slopes and widths of lines, such data including information indicative of raster data for portions of lines of the predetermined slopes and widths. The stored data associated with the slope and width of the line to be rasterized is accessed, and raster data for one of predetermined portions of the line to be rasterized is generated from the accessed data, wherein the predetermined portions collectively form the line to be rasterized. The generated raster data is copied to a bitmap memory, and the steps of generating and copying raster data are repeated until the entire line has been rasterized.

Abstract: Apparatus for cooling an electronic circuit module includes a heat sink in thermal contact with the circuit module and a device for directing cooling gas at the heat sink. The heat sink includes multiple fins defining channels between them, a base having a surface for contact with the circuit module, and a plurality of passages located between the fins and the base and interconnecting with the channels. At least a part of the cooling gas flows between the fins and absorbs thermal energy from the fins and then flows through the passages and absorbs additional thermal energy. The fins and the passages provide a large area of contact with the cooling air and reduce the pressure drop through the heat sink. The heat sink provides a path for efficient conduction of thermal energy from the circuit module to the fins and prevents the formation in the cooling air of recirculating eddies which can reduce heat transfer.

Abstract: A computing system controlling is presented which controls input from both a keyboard and a touchscreen. Photo detectors placed in rows and columns along the edge of the touchscreen detect light beams directed across a surface on the touchscreen. The touchscreen indicates to the computing system controller addresses of which detectors do not detect light beams because an object is blocking the light beam path. The computing system controller calculates an average for the row addresses of detectors not detecting light beams, and an average for the column addresses of detectors not detecting light beams. The average is then sent to the host program.

Abstract: An edge generation circuit phase delays pulses of a first signal propagated on an integrated circuit. The edge generation circuit includes a first variable delay circuit located on the integrated circuit, a delay line located off the integrated circuit and a second variable delay circuit located on the integrated circuit. The first variable delay circuit receives the first signal and produces a second signal which is in phase with the first signal. The delay line receives the second signal and produces a third signal. The third signal is delayed in phase from the second by a precise amount. The second variable delay circuit receives the third signal from the delay line and produces a fourth signal. The fourth signal is in phase with the third signal.

Abstract: A carriage for a scanning ink jet plotter has at least two roller supports which ride on the platen or on the drafting surface to maintain a constant spacing between an ink jet mounted on the carriage and the drafting surface to improve resolution of the plotted lines. A biasing spring may also be used the urge the roller supports into contact with the drafting surface for further enhanced resolution.

Abstract: In an X-Y addressable workpiece positioner the workpiece to be positioned, such as a semiconductive wafer to be aligned with a mask image, is coupled to move with a work stage moveable in X and Y direction and having a two-dimensional array of positioning indicia affixed thereto for movement therewith. An enlarged image of a portion of the positioning array is projected onto a relatively stationary sensor stage to derive an output determinative of the X and Y coordinates of the positioning array relative to the position of the sensor. The sensed X and Y coordinates of the positioning array are compared with the X and Y coordinates of a reference positioning address to derive an error output. The work stage is moved in response to the error output for causing the workpiece to be positioned to the reference address.

Abstract: A device, particularly useful for thermal ink-jet printheads, for improving the repeatability of droplet volume is disclosed. Offsetting a nozzle from its corresponding ink heating element perpendicularly to the flow if ink across the element has been found to significantly reduce the ejected droplet volume deviation.

Abstract: The quality of the images of dot printers such as ink jet printers (20) is improved by spacing the ink jet nozzles (52) of the print head (50) by an amount greater than the pixel spacing of the printing medium (22), and operating the sources in a manner such that adjacent pixels are not printed until the deposited colorant has time to dry. In the traversing direction (39), neighboring pixels are not printed on the same traversing pass. In the advance direction (32), by making the spacing of the ink jet nozzles (52) an integer multiple of the pixel spacing and advancing the print head (50) by a different integer multiple of the pixel spacing, the pixel patterns can be readily printed with high printing volume and with a constant incremental advance of the print head. The present approach is applicable to both color and black-and-white printing, but particular improvement is found for color printing.

Abstract: A scan testable circuit in a computer system is controlled by using a single scan clock and a fixed delay circuit to realize the required scan clocks and a required scan mode enable signal. The multiple signals are generated from a subset of signals supplied to the scan control signal generation circuit. System data and scan data are routed through a multiplexer to test or initialize lines and circuitry. A scan control signal generation circuit according to the invention has the advantage of eliminating as excess a scan mode enable signal originating elsewhere in the computer system, thereby eliminating unneeded signal traces while minimizing the number of pins required for this function. In a first embodiment, a scan mode enable signal is generated from one of two scan clocks. In a second embodiment, both scan clocks and the scan mode enable signal are generated from a single source clock.

Abstract: An ink delivery system (1) for delivering ink to a print head comprising an ink supply bag (3), an ink regulating bag (5), a three way valve (7), a print head (19), pipes (11, 13, 15) to transfer selectively ink from the supply bag to the regulating bag or from the regulating bag to the print head. The regulating bag is at a lower level than the print head.

Abstract: A computer having a file management system is presented. The file management system includes a plurality of application programs, a plurality of data files, a plurality of class data structures and a plurality of object data structures. Each class data structure includes a reference to an application program within the plurality of application programs. Each object data structure includes a reference to a class data structure from the plurality of class data structure and a reference to at least one data file from the plurality of data files.The use of object data structures adds a layer between a user of the computer and data files. This allows for the computer to refer to an object data structure and associated access files using a tag which is inaccessible to the user. The user refers to an object based on the physical location of the object on the screen. The user may also give the object data structure a name, which is wholly unconnected to the value of the tag.

Abstract: A system uses variable ranges to support symbolic debugging of optimized code. A debug symbol table is constructed which includes descriptions of each user resource in source code. Additionally, a range table is constructed. The range table contains, for each user resource which is stored in numerous locations during execution of the code, a list of ranges and a description of where the user resource may be found during each range. If the user resource is stored as a constant during a particular range, the value of the constant may be stored in the range table. The description of each user resource in the debug symbol table includes a flag which indicates whether there is a list of ranges in the range table for a particular user resource. If there is, the description of the particular user resource will include a pointer to the list of ranges for that user resource.

Abstract: In a computing system a method for performing a multiplication of a first multiplicand and a second multiplicand is presented. The computing system includes a plurality of registers, an instruction decoder, an arithmetic logic unit, and a preshifter. The first multiplicand is divided into a plurality of equal length sections. Each section includes "n" bits, where "n" is an integer greater than one. The second multiplicand is placed in a first register from the plurality of registers. A second register from the plurality of registers is cleared to zero. For each section from the plurality of sections, starting with a first section containing high order bits of the first multiplication and proceeding to a last section of the first multiplicand containing low order bits of the first multiplicand the following three substeps. First, when the low order bit of a current section is a "1", the contents of the first register are added to the contents of the second register via the arithmetic logic unit.