Abstract: An apparatus and method for synchronizing a cache mode in a cache memory system in a computer to protect cache operations. The cache memory system has a first controller and a second controller and two cache modules and operates in a plurality of cache modes. The cache mode is stored as metadata in the cache modules and is detected by the first controller to determine the cache mode. Lock signals in the first controller are set in accordance with the cache mode detected to set the cache mode state in the first controller. The second controller copies the cache mode state from the first controller to synchronize both controllers in the same cache mode state. After a failure of the second controller, the first controller may lock access to both caches to recover data previously accessed by the second controller. The second controller restarts and copies the cache mode state from the first controller, so that both controllers return to the cache mode state prior to the failure of the second controller.

Abstract: A cache memory system is enabled into one of a plurality of cache modes in a cache memory system in a computer. The cache memory system has a first controller and two cache memories, the cache memories are partitioned into quadrants with two quadrants in each cache memory. A cache mode detector in the first controller detects a mirror cache mode set for the cache memory system. An address enabler in the first controller enables access to first pair of quadrants, one quadrant in each cache memory, in response to detection of a mirror cache mode. A second controller follows the cache mode set by the cache mode detector and has an address enabler. The address enabler in the second controller enables access to both quadrants in one cache memory in a non-mirror cache mode, and enables the access to a second pair of quadrants, one quadrant in each cache memory, in response to detection of a mirror cache mode by said cache mode detector.

Abstract: Methods for handling exceptions caused by speculatively scheduled instructions or predicated instructions executed within a computer program are described. The method for speculatively scheduled instructions includes checking at a commit point of a speculatively scheduled instruction, a semaphore associated with the speculatively scheduled instruction and branching to an error handling routine if the semaphore is set. A set semaphore indicates that an exception occurred when the speculatively scheduled instruction was executed. For a predicated instruction the method includes checking a predicate of an eliminated branch and a semaphore associated with the speculative instruction at a commit point of the speculative instruction and branching to an error handling routine if the semaphore indicates that an exception occurred when said speculative instruction was executed, and the predicate is true, which indicates that said speculative instruction was properly executed.

Abstract: A method of providing conversion from YUV signals to RGB signals includes the steps of determining a correspondence value between each of the Y, U, and V pixel values and the corresponding one of the R, G, and B pixel values. Three tables are generated; a Y table, a U table and a V table. During operation, each table may then be easily accessed by indexing the table with the respective Y, U or V input, to provide R,G,B data. The method may be used in a 64 bit embodiment using two registers or one register. Alternatively, the method may be used in a 32 bit embodiment. The conversion method can easily be augmented to provide color adjustment during conversion without any added complexity.

Abstract: A very thin portable computer includes a computer housing for holding electronic components and a battery housing movably mounted external to the computer housing, the battery housing adapted for holding batteries for supplying power to the electronic components. The battery housing is rotatably mounted on the computer housing such that the battery housing rotates between a closed position wherein the battery housing covers the rear side of the computer and an open position wherein the battery housing exposes connectors on the computer housing and elevates the rear side of the computer housing to an angle convenient for typing.

Abstract: In a method and system for dynamically improving the performance of a server in a network, a tuning system monitors a workload of the server in real time, monitors a set of internal performance characteristics of the server in real time, and monitors a set of adjustable server parameters of the server in real time. The workload of the server may include the frequency and type of service requests received by the server from clients in the network. The internal server performance characteristics may include, for example, a data cache hit ratio of a data cache in the server. The set of server parameters may include, for example, the overall data cache size or the data cache geometry of the server. The tuning system periodically alters one or more of the set of adjustable server parameters as a function of the workload and internal performance characteristics of the server.

Abstract: In a method and system for dynamically improving the performance of a server in a network, a tuning system monitors a workload of the server in real time, monitors a set of internal performance characteristics of the server in real time, and monitors a set of adjustable server parameters of the server in real time. The workload of the server may include the frequency and type of service requests received by the server from clients in the network. The internal server performance characteristics may include, for example, a data cache hit ratio of a data cache in the server. The set of server parameters may include, for example, the overall data cache size or the data cache geometry of the server. The tuning system periodically alters one or more of the set of adjustable server parameters as a function of the workload and internal performance characteristics of the server.

Abstract: A data block in a RAID array is reconstructed under the control of metadata recorded on the RAID array. The RAID array has a plurality of members, each member being a data storage device. The metadata includes device metadata for data blocks recorded on each member and RAIDset metadata for RAID protected data blocks recorded across the members of the RAID array. The RAID protected data blocks include user data blocks, RAIDset metadata blocks and parity data blocks. The data blocks are reconstructed by detecting from a device FE bit in the device metadata that a bad data block corresponding to or associated with the device FE bit needs to be reconstructed. The data is read from each data block, other than the bad data block, in the same RAID sliver with bad data block. A RAID sliver of data blocks includes all the data blocks in a RAID protected sliver of data blocks.

Abstract: A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3 times booth recode multiplication. The multiplier includes logic to determine a fast sign extend to replace bit positions shifted in the array as well as a rounding adder to provide a rounded result while determining the final result from the booth recode multiplier. The multiplier also includes a circuit to determine a contribution to the final multiplication result from a lower order product with out forming the entire product.

Abstract: Apparatus and a related method for managing entities in a complex and, in general, geographically distributed system, such as distributed data processing system. The management approach is defined in terms of a generalized model having management modules integrated into a single cooperative system by a management director kernel. The management modules include presentation modules to provide an interface with users who manage the complex system, access modules to provide an interface with managed entities or devices, and function modules to define various functions that may be performed in controlling or monitoring the managed entities. If the complex system being managed is large, a managed entity and an associated access module may be located on one physical system, while a presentation module is located on another physical system, close to the user, and a function module being used might be located on yet another physical system, for reasons of processing convenience.

Abstract: A printer architecture utilizing network resources to distribute printer controller and translator functions and thereby process several print jobs in parallel. The several print jobs can be transferred, in order of completion, to a print engine for a high speed real time printing operation, or stored as pre-rasterized images for subsequent access and delivery to the print engine.

Abstract: The present invention is a method of writing data to a storage system using a redundant array of independent/inexpensive disks ("RAID") organization that eliminates the write hole problem of regenerating undetected corrupt data. The invention also overcomes the need for system overhead to synchronize data writes to logical block numbers that map to the same parity block. A log is constructed and used for storing information relating to requested updates or write operations to the data blocks in the multiple disk array. A separate entry is made in the log for each parity block that must be updated as a result of the write operation. Each log entry contains the addresses of the logical block numbers to which data must be written for that operation. After the new data is written to data blocks in the RAID array, a background scrubber operation sequentially reads the next available entry in the log and performs a parity calculation to determine the parity resulting from the write operation.

Abstract: A graphical figure is defined. A library of simple tasks is created using trial stimulus/response combinations. A hill climbing algorithm is employed to find a stimulus/response combination that accomplishes an optimum result for each task. An animation editor facilitates the creation of composite animated sequences by causing the retrieving and displaying of a first simple task, controlling the length of time the first simple task is displayed and by causing the retrieving and displaying of additional simple tasks and controlling the length of time the additional simple tasks are displayed.

Abstract: A new class of purpose computers called Programmable Reduced Instruction Set Computers (PRISC) use RISC techniques a basis for operation. In addition to the conventional RISC instructions, PRISC computers provide hardware programmable resources which can be configured optimally for a given user application. A given user application is compiled using a PRISC compiler which recognizes and evaluates complex instructions into a Boolean expression which is assigned an identifier and stored in conventional memory. The recognition of instructions which may be programmed in hardware is achieved through a combination of bit width analysis and instruction optimization. During execution of the user application on the PRISC computer, the stored expressions are loaded as needed into a programmable functional unit. Once loaded, the expressions are executed during a single instruction cycle.

Abstract: In a method and system for dynamically improving the performance of a server in a network, a tuning system monitors a workload of the server in real time, monitors a set of internal performance characteristics of the server in real time, and monitors a set of adjustable server parameters of the server in real time. The workload of the server may include the frequency and type of service requests received by the server from clients in the network. The internal server performance characteristics may include, for example, a data cache hit ratio of a data cache in the server. The set of server parameters may include, for example, the overall data cache size or the data cache geometry of the server. The tuning system periodically alters one or more of the set of adjustable server parameters as a function of the workload and internal performance characteristics of the server.

Abstract: A digital phase lock loop synchronizes a first signal to a second signal having a predefined frequency. The first signal usually has an instantaneous frequency greater than the predefined frequency, so that the first signal is constantly gaining phase with respect to the second signal. The digital phase lock loop performs periodic correction cycles by detecting a predefined phase relationship between the first signal and the second signal, and when the predefined phase relationship is detected, expanding the first signal in phase by a predetermined amount. Preferably, the first signal is generated by clocking a frequency divider with a clocking frequency, and the first signal is expanded in phase by inhibiting the clocking of the frequency divider for one clocking cycle for each correction cycle. Preferably, the predetermined phase relationship is detected when the second signal has a predetermined logic state coincident with clocking by the clocking signal and a predetermined state of the frequency divider.

Abstract: A computer system including a cache which has a wave pipeline read controller is described. The system in addition to the cache memory includes a processor coupled to the cache memory. The processor includes a register stack which stores values corresponding to a wave number and read speed which is loaded as part of a configuration of the processor. The processor determines a repetition rate for read data corresponding to a difference between the values of read speed and wave number. The processor includes a logic delay line comprised of a plurality of clock delay elements, each of said elements providing successively increasing discrete delays to a clock signal fed to the logic delay line. The delay line is used to provide inputs to a first and second multiplexer which are respectively controlled by a signal corresponding to a desired repetition rate for read cycles and a signal corresponding to the read speed of the cache memory.

Abstract: A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process.

Abstract: A method for translating a boolean function into a logic circuit using gates from a standard library is provided. The method includes the steps of translating the boolean function into a network comprising a plurality of sub-trees, where each of the sub-trees represents a portion of the function, and where each sub-tree includes a plurality of representations for that portion of the function. The plurality of representations are stored in an alterative logic diagram, which comprises a plurality of ugates. The ugates are data structures which define the inputs and the connectivity of the respective ugate in the sub-tree. The sub-tree is mapped to gates from the standard library by selecting the best sub-tree representation. Accordingly, an improved method of logic synthesis is provided that allows for the optimal representation to be provided by starting with a wider range of inputs to the mapping process.

Abstract: A cache memory system in a computing system has a first cache module storing data, a second cache module storing data, and a controller writing data simultaneously to both the first and second cache modules. A second controller can be added to also write data simultaneously to both the first and second cache modules. In a single write cycle each controller requests access to both the first and second cache modules. Both cache modules send an acknowledgement of the cache request back to the controllers. Each controller in response to the acknowledgements from both of the cache modules simultaneously sends the same data to both cache modules. Both of the cache modules write the same data into cache in their respective cache modules.