Abstract: A method for translating a boolean function into a logic circuit using gates from a standard library is provided. The method includes the steps of translating the boolean function into a network comprising a plurality of sub-trees, where each of the sub-trees represents a portion of the function, and where each sub-tree includes a plurality of representations for that portion of the function. The plurality of representations are stored in an alterative logic diagram, which comprises a plurality of ugates. The ugates are data structures which define the inputs and the connectivity of the respective ugate in the sub-tree. The sub-tree is mapped to gates from the standard library by selecting the best sub-tree representation. Accordingly, an improved method of logic synthesis is provided that allows for the optimal representation to be provided by starting with a wider range of inputs to the mapping process.

Abstract: A cache memory system in a computing system has a first cache module storing data, a second cache module storing data, and a controller writing data simultaneously to both the first and second cache modules. A second controller can be added to also write data simultaneously to both the first and second cache modules. In a single write cycle each controller requests access to both the first and second cache modules. Both cache modules send an acknowledgement of the cache request back to the controllers. Each controller in response to the acknowledgements from both of the cache modules simultaneously sends the same data to both cache modules. Both of the cache modules write the same data into cache in their respective cache modules.

Abstract: Information is stored in temporary storage and subsequently transferred to a memory over a bus. The temporary storage is provided with a plurality of entries each of which has a selected size that is smaller than a size of the bus. Information that is designated for a common area of the memory is stored in different entries, and the different entries are linked. Before being transferred to memory, the information from linked entries is assembled. The assembled information is then transferred over the bus to memory. Embodiments of the temporary storage include a write queue and a write buffer.

Abstract: A data processing system includes at least one central processor for executing instructions of software programs. In addition the data processing system includes a memory containing a data structure common to the software programs. The common data structure includes a compressed index data structure. The index structure stores index entries referencing a database. The database includes multiple records, each having a unique address in the database. Each index entry includes a word entry if the index entry represents a compressed encoding of a unique portion of information sequentially parsed from the database. The word entry is followed by one or more location entries which reference occurrences of the portions of information. Each index entry includes a metaword entry if the index entry represents a unique attribute of one or more related words. The metaword entry is followed by one or more location entries referencing occurrences of the attributes.

Abstract: An apparatus is described to provide a fault tolerant power-on of a computer system, using a BIOS memory containing a primary power-on system level configuration program for a computer system and a separate memory which contains a subset of the primary power-on system level configuration program. The subset program is accessed automatically, without human intervention, responding to a checksum detector of the BIOS memory data.

Abstract: A method and apparatus performs high speed forward or reverse Discrete Cosine Transform (DCT) for video compression and decompression that is optimized in both directions and which uses minimal hardware. This invention can be used to improve the speed of electronic transmission of images, decrease the electronic bandwidth necessary to transmit images electronically, increase the density of electronic storage of images, and speed up image enhancement operations.

Abstract: A computer system includes a housing, a motherboard, a first module and a second module. An electrical connector on the motherboard is joined to and in electrical communication with an electrical connector on one of two opposing surfaces of the first module, and an electrical connector on the second module is joined to and in electrical communication with another electrical connector on the other of the opposing surfaces of the first module. An electrically conductive path connects the two electrical connectors on the opposing surfaces of the first module. The motherboard transmits electrical signals corresponding to a module identifier to the first module through the motherboard's joined electrical connector. An electrical device on the first module in the electrically conductive path modifies the electrical signals so that they correspond to a second module identifier.

Abstract: Automatic shelf-to-shelf address assignment is provided for a plurality of disk drive supporting shelves that are removably contained within a multi--shelf cabinet. Error detection apparatus detects failure in the automatic assignment of shelf addresses. An address input of shelf-N receives a shelf addressing voltage from shelf N+1. Shelf-N checks to ensure that the received shelf-N address voltage is within a correct range. Where-N now increases its shelf-N address by one and applies this incremented address to an address input of shelf-N+1. Accuracy of the shelf-N+1 address input is checked, as are the cable/connectors that connect shelf-N to shelf-N+1. ADC and ADC techniques are used, and operation of the automatic address assignment system is timed.

Abstract: Provided herein is a method and apparatus for host transparent storage controller failover and failback. A controller is capable of assuming the identity of a failed controller while continuing to respond to its own SCSI ID or IDs in such a way that all SCSI IDs and associated units (LUNS) of the failed controller are effectively taken over by the surviving controller. This "failover" behavior is transparent to any attached host computers and is treated by such attached hosts as a powerfail condition. The symmetric operation of returning the targets (IDs) and units (LUNs) to the previously failing controller ("failback") is likewise transparent.

Abstract: In a computer network, a method of random sampling of network packets is provided including the steps of providing a network switch, providing a monitoring device, the monitoring having a memory and a data storage unit, providing a network interface to connect the network switch to the monitoring switch, selecting a reference error check code value in the monitoring device, receiving a first network packet from the network switch, comparing, in the network monitoring device, the reference error check code with an error check code of a first network packet, storing the first network packet in the monitoring device if the error check code value of the first network packet matches the reference error check code of the first network packet, and repeating the steps of receiving, comparing and storing for subsequent network packets.

Abstract: Disclosed are multilayer electrical structures comprising a discrete, partially-cured, microsphere-filled resin layer, and a method for fabricating such multilayer electrical structures using a carrier member to support and introduce the microsphere-filled resin layer.

Abstract: A novel scheduling method is provided which may be used for rate-based scheduling (e.g., for scheduling flows at some assigned rates in a computer network) or for weighted fair sharing of a common resource (e.g., scheduling weighted jobs in a processor). The method is based on hierarchical application of Relative Error (RE) scheduling. The present method of a Hierarchical RE Scheme (HRE) with complexity O(log(N)), where N is the maximum number of jobs supported by the scheduler, is provided.

Abstract: A circuit board retainer for use within an enclosure for guiding and securing a circuit board within the enclosure includes a guide portion having an upper rail and a lower rail extending along an edge of the circuit board retainer forming a slot therebetween for guiding a side of the circuit board. A latching portion positioned adjacent to the guide portion engages an ejector lever pivotably connected to the circuit board. The ejector lever is capable of locking the circuit board in place relative to the circuit board retainer.

Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.

Abstract: Disclosed is a method and apparatus for reconstructing data in a computer system employing a modified RAID 5 data protection scheme. The computer system includes a write back cache composed of non-volatile memory for storing (1) writes outstanding to a device and associated data read, and (2) storing metadata information in the non-volatile memory. The metadata includes a first field containing the logical block number or address (LBN or LBA) of the data, a second field containing the device ID, and a third field containing the block status. From the metadata information it is determined where the write was intended when the crash occurred. An examination is made to determine whether parity is consistent across the slice, and if not, the data in the non-volatile write back cache is used to reconstruct the write that was occurring when the crash occurred to insure consistent parity, so that only those blocks affected by the crash have to be reconstructed.

Abstract: An architecture, module set and platform to provide total power protection from utility disturbances. Power supplies employing the invention are built on power buses for utility AC input, battery DC input and conditioned AC output housed in the platform and employ modular line-to-AC-or-DC power-factor-correcting converters and battery/charger sets either housed in the platform or integrated as part of the front end power supply for a critical load such as a computer.

Abstract: An apparatus and method of implementing an enhanced PCI interrupt controller which accommodates the industry standard wire-or functionality. With such an arrangement a method and apparatus to identify a source of a PCI interrupt without the need for polling is implemented with a register-based architecture and staged initiator decode. The invention implements both the default industry standard and a non-polled (interrupt accelerator) mode.

Abstract: Disclosed herein is a stacked skip list data structure for maintaining select nodes on multiple lists. The data structure includes a primary and a secondary skip list of nodes. Each node in the primary skip list uses at least one forward pointer in a primary array of forward pointers and provides a node level field for storing the level of such node, the level determined by the number of pointers being used. A secondary skip list is stacked on the primary skip list of nodes. It includes a subset (zero or more nodes) occurring on the primary skip list and utilizes zero or more unused forward pointers in the primary array as its forward pointers. Thus, a system agent performing operations on the secondary skip list utilizes the node level in the node level field as an index into the primary array of forward pointers to locate the secondary array of forward pointers.

Abstract: A mechanism for performing retroactive backups in a computer system is presented. The retroactive backup mechanism employs a backup policy dictating that certain backups are to be performed at set times and for set backup levels, but subject to user-defined selection criteria so that the backups are of a retroactive nature. The selection criteria comprises a retroactive backup date upon which the scheduled backup is made effective. It is selected to correspond to the backup date of a previous backup or save set. Alternatively, the retroactive backup date upon which the scheduled backup is made effective is determined by controlling the amount of data to be backed up. Thus, the selection criteria comprises a maximum size threshold, selected by a user or system administrator as the amount of data that can be backed up in an allotted backup time. The retroactive backup copies to a new save set only data that has not been modified or deleted since the date indicated as the retroactive backup date.

Abstract: Programs to be executed on a distributed computer system are instrumented to allow data sharing. The distributed computer system includes a plurality of workstations. Each workstation includes a processor, a memory having addresses, and an input/output interface connected to each other by a bus, the input/output interfaces connecting the workstations to each other by a network. A set of virtual addresses assigned to the memories are allocated to store a shared data structure as one or more blocks accessible by instructions of programs executing in any of the processors. The size of a particular allocated block can vary with the shared data structure. Each block includes an integer number of lines, and each line including a predetermined number of bytes. Prior to executing the programs, the programs are statically analyzed to locate instructions that access the shared data stored at target addresses of the lines of the one or more blocks.