Patents Represented by Attorney, Agent or Law Firm Ronald J. Meetin
  • Patent number: 8163619
    Abstract: An asymmetric insulated-gate field effect transistor (100U or 102U) is provided along an upper surface of a semiconductor body so as to have first and second source/drain zones (240 and 242 or 280 and 282) laterally separated by a channel zone (244 or 284) of the transistor's body material. A gate electrode (262 or 302) overlies a gate dielectric layer (260 or 300) above the channel zone. A pocket portion (250 or 290) of the body material more heavily doped than laterally adjacent material of the body material extends along largely only the first of the S/D zones and into the channel zone. The vertical dopant profile of the pocket portion is tailored to reach a plurality of local maxima at respective locations (PH-1-PH-3-NH-3) spaced apart from one another. This typically enables the transistor to have reduced current leakage.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: April 24, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Jeng-Jiun Yang, Constantin Bulucea, Sandeep R. Bahl
  • Patent number: 8148777
    Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 500, 510, or 530; or 220, 220W, or 540) is provided with a hypoabrupt vertical dopant profile below one (104; or 264 or 564) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108; or 268 or 568). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: April 3, 2012
    Assignee: National Semiconductor Corporation
    Inventor: Constantin Bulucea
  • Patent number: 8129262
    Abstract: Fabrication of an insulated-gate field-effect transistor (110) entails separately introducing three body-material dopants, typically through an opening in a mask, into body material (50) of a semiconductor body so as to reach respective maximum dopant concentrations at three different vertical locations in the body material. A gate electrode (74) is subsequently defined after which a pair of source/drain zones (60 and 62), each having a main portion (60M or 80M) and a more lightly doped lateral extension (60E or 62E), are formed in the semiconductor body. An anneal is performed during or subsequent to introduction of semiconductor dopant that defines the source/drain zones. The body material is typically provided with at least one more heavily doped halo pocket portion (100 and 102) along the source/drain zones. The vertical dopant profile resulting from the body-material dopants alleviates punchthrough and reduces current leakage.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: March 6, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Constantin Bulucea, Fu-Cheng Wang, Prasad Chaparala
  • Patent number: 8118715
    Abstract: An exercise machine suitable for exercising a person's muscles contains a frame (100Y), a seat (102) situated over the frame, a seatback (104), a connection mechanism (106Y) for flexibly and adjustably connecting the seatback to the frame or/and the seat, and a pedaling mechanism (112Y) connectable to the frame and having a pair of movable foot pedals (140). The connection mechanism includes (a) a seatback-attaching portion (120, 180, 184, 186, 188, and 190) attached to the seatback and (b) a support rod (128Y) extending between the seatback-attaching portion and a location within the frame. The support rod is of adjustable length for adjusting the incline of the seatback to the seat. The seatback can swivel about a swivel axis of the connection mechanism. The exercise machine normally has a pair of frame legs (302).
    Type: Grant
    Filed: August 3, 2007
    Date of Patent: February 21, 2012
    Assignee: Ab Rider L.L.C.
    Inventors: Donald D. Greene, Ronald J. Meetin
  • Patent number: 8101479
    Abstract: A gate electrode (302) of a field-effect transistor (102) is defined above, and vertically separated by a gate dielectric layer (300) from, a channel-zone portion (284) of body material of a semiconductor body. Semiconductor dopant is introduced into the body material to define a more heavily doped pocket portion (290) using the gate electrode as a dopant-blocking shield. A spacer (304T) having a dielectric portion situated along the gate electrode, a dielectric portion situated along the body, and a filler portion (SC) largely occupying the space between the other two spacer portions is provided. Semiconductor dopant is introduced into the body to define a pair of source/drain portions (280M and 282M) using the gate electrode and spacer as a dopant-blocking shield. The filler spacer portion is removed to convert the spacer to an L shape (304). Electrical contacts (310 and 312) are formed respectively to the source/drain portions.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: January 24, 2012
    Assignee: National Semiconductor Corporation
    Inventors: D. Courtney Parker, Donald M. Archer, Sandeep R. Bahl, Constantin Bulucea, William D. French, Peter B. Johnson, Jeng-Jiun Yang
  • Patent number: 8034679
    Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) is fabricated so as to have a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone, normally serving as the drain, and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material is preferably provided with a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262) normally serving as the source.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: October 11, 2011
    Assignee: National Semiconductor Corporation
    Inventor: Constantin Bulucea
  • Patent number: 8030151
    Abstract: A bipolar transistor (101) has a base (243) formed with an intrinsic base portion (2431), a base contact portion (245C), and a base link portion (243L) that extends between the intrinsic base portion and the base contact portion. An isolating dielectric layer (267-1 or 267-2) is provided above the base link portion. The length of the base link portion is determined, and thereby controlled, with a lateral spacing portion (269-1 or 269-2) of largely non-monocrystalline semiconductor material, preferably polycrystalline semiconductor material, provided on the dielectric layer above the base link portion. The lateral spacing portion is typically provided as part of a layer of non-monocrystalline semiconductor material used in the gate electrode of an insulated-gate field-effect transistor.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: October 4, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Jeng-Jiun Yang, Constantin Bulucea
  • Patent number: 8013390
    Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) has a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material preferably includes a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262).
    Type: Grant
    Filed: November 4, 2010
    Date of Patent: September 6, 2011
    Assignee: National Semiconductor Corporation
    Inventor: Constantin Bulucea
  • Patent number: 8005135
    Abstract: An analog equalizer (613 and 614) adaptively equalizes an input analog signal affected with intersymbol interference (“ISI”), or an intermediate analog signal generated therefrom, to produce a filtered partially equalized analog signal with reduced ISI. An analog-to-digital converter (210) converts the filtered analog signal, or an intermediate analog signal generated therefrom, into an initial digital signal. A digital equalizer (212) adaptively equalizes the initial digital signal, or an intermediate digital signal generated therefrom, to produce an equalized digital signal as a stream of equalized digital values with further reduced ISI. An output decoder (605) decodes the equalized digital values, or intermediate digital values generated therefrom, into a stream of symbols.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: August 23, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Tulsi Manickam, Peter J. Sallaway, Sreen A. Raghavan, Abhijit M. Phanse, James B. Wieser
  • Patent number: 7973372
    Abstract: An insulated-gate field-effect transistor (100) provided along an upper surface of a semiconductor body contains a pair of source/drain zones (240 and 242) laterally separated by a channel zone (244). A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. Each source/drain zone includes a main portion (240M or 242M) and a more lightly doped lateral extension (240E or 242E) laterally continuous with the main portion and extending laterally under the gate electrode. The lateral extensions, which terminate the channel zone along the upper semiconductor surface, are respectively largely defined by a pair of semiconductor dopants of different atomic weights. With the transistor being an asymmetric device, the source/drain zones constitute a source and a drain. The lateral extension of the source is defined with dopant of higher atomic weight than the lateral extension of the drain.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: July 5, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Sandeep R. Bahl, William D. French, Constantin Bulucea
  • Patent number: 7972918
    Abstract: A semiconductor structure is provided with (i) an empty well having relatively little well dopant near the top of the well and (ii) a filled well having considerably more well dopant near the top of the well. Each well is defined by a corresponding body-material region (108 or 308) of a selected conductivity type. The regions respectively meet overlying zones (104 and 304) of the opposite conductivity type. The concentration of well dopant of the selected conductivity type locally reaches a maximum in each body-material region at a location no more than 10 times deeper below the upper semiconductor surface than the overlying zone's depth, decreases by at least a factor of 10 in moving from the empty-well maximum-concentration location through the overlying zone to the upper surface, and reaches at least one other maximum in moving from the filled-well maximum-concentration location through the other zone to the upper surface.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: July 5, 2011
    Assignee: National Semiconductor Corporation
    Inventor: Constantin Bulucea
  • Patent number: 7968921
    Abstract: An asymmetric insulated-gate field-effect transistor (100) has a source (240) and a drain (242) laterally separated by a channel zone (244) of body material (180) of a semiconductor body. A gate electrode (262) overlies a gate dielectric layer (260) above the channel zone. A more heavily doped pocket portion (250) of the body material extends largely along only the source. Each of the source and drain has a main portion (240M or 242M) and a more lightly doped lateral extension (240E or 242E). The drain extension is more lightly doped than the source extension. The maximum concentration of the semiconductor dopant defining the two extensions occurs deeper in the drain extension than in the source extension. Additionally or alternatively, the drain extension extends further laterally below the gate electrode than the source extension. These features enable the threshold voltage to be highly stable with operational time.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: June 28, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Constantin Bulucea, William D. French, Sandeep R. Bahl, Jeng-Jiun Yang, D. Courtney Parker, Peter B. Johnson, Donald M. Archer
  • Patent number: 7936020
    Abstract: A two-terminal ESD protection structure formed by an arrangement of five adjacent semiconductor regions (112, 114, 116, 118, and 120) of alternating conductivity type provides protection against both positive and negative ESD voltages. The middle semiconductor region electrically floats. When the two terminals (A and K) of the ESD protection structure are subjected to an ESD voltage, the structure goes into operation by triggering one of its two inherent thyristors (170 and 180) into a snap-back mode that provides a low impedance path through the structure for discharging the ESD current.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: May 3, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Albert Z. H. Wang, Chen H. Tsay, Peter Deane
  • Patent number: 7879669
    Abstract: At least one source/drain zone (140, 142, 160, or 162) of an enhancement-mode insulated-gate field-effect transistor (120 or 122) is provided with graded junction characteristics to reduce junction capacitance, thereby increasing switching speed. Each graded junction source/drain zone contains a main portion (140M, 142M, 160M, or 162M) and a more lightly doped lower portion (140L, 142L, 160L, or 162L) underlying, and vertically continuous with, the main portion. The magnitudes of the threshold voltages of a group of such transistors fabricated under the same post-layout fabrication process conditions so as to be of different channel lengths reach a maximum absolute value VTAM when the channel length is at a value LC, are at least 0.03 volt less than VTAM when the channel length is approximately 0.3 ?m greater than LC, and materially decrease with increasing channel length when the channel length is approximately 1.0 ?m greater than LC.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: February 1, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Chih Sieh Teng, Constantin Bulucea, Chin-Miin Shyu, Fu-Cheng Wang, Prasad Chaparala
  • Patent number: 7863681
    Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) has a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material preferably includes a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262).
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: January 4, 2011
    Assignee: National Semiconductor Corporation
    Inventor: Constantin Bulucea
  • Patent number: 7838369
    Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) is fabricated so as to have a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material is preferably provided with a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262).
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: November 23, 2010
    Assignee: National Semiconductor Corporation
    Inventor: Constantin Bulucea
  • Patent number: 7838930
    Abstract: An insulated-gate field-effect transistor (500, 510, 530, or 540) has a hypoabrupt step-change vertical dopant profile below one (104 or 564) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 568). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material largely undergoes a step increase by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: November 23, 2010
    Assignee: National Semiconductor Corporation
    Inventor: Constantin Bulucea
  • Patent number: 7785971
    Abstract: Fabrication of complementary first and second insulated-gate field-effect transistors (110 or 112 and 120 or 122) from a semiconductor body entails separately introducing (i) three body-material dopants into the body material (50) for the first transistor so as to reach respective maximum dopant concentrations at three different locations in the first transistor's body material and (ii) two body-material dopants into the body material (130) for the second transistor so as to reach respective maximum dopant concentrations at two different locations in the second transistor's body material. Gate electrodes (74 or 94 and 154 or 194) are subsequently defined after which source/drain zones (60, 62 or 80, 82 and 140, 142 or 160, 162) are formed in the semiconductor body. The vertical dopant profiles resulting from the body-material dopants alleviate punchthrough and reduce current leakage.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: August 31, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Constantin Bulucea, Fu-Cheng Wang, Prasad Chaparala
  • Patent number: 7756228
    Abstract: Analog echo-cancelling circuitry (611 and 627) operates on an input analog signal that includes an echo of an output signal, or on an analog signal generated from the input signal, to produce an analog signal with reduced echo. An analog-to-digital converter (210) converts the echo-reduced analog signal, or an analog signal generated therefrom, into a digital signal. Digital echo-cancelling circuitry (615 and 621) operates on the digital signal, or on a digital signal generated therefrom, to produce a digital signal with further reduced echo. An output decoder (605) decodes the echo-reduced digital signal, or a digital signal generated therefrom, into a stream of symbols. The echo-filtering characteristics of both echo-cancelling circuitries are typically adaptively adjusted during generation of the symbol stream. The analog echo-filtering characteristics may be adapted in response to information provided by operating on the echo-reduced digital signal or on a digital signal generated therefrom.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: July 13, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Tulsi Manickam, Peter J. Sallaway, Sreen A. Raghavan, Abhijit M. Phanse, James B. Wieser
  • Patent number: 7719862
    Abstract: A power factor correction circuit (42/44) responsive to an input power supply signal at an input supply voltage (VAC) that varies largely sinusoidally with time at a fundamental supply frequency contains regulator/control circuitry (60, 62, and 64) for measuring and removing overtones (ILDm or IFWRm) in the input supply current (ILD) or in a rectified form (IFWR) of the input supply current. Each overtone is expressible as the product of an amplitude component (Im) and a sinusoidal function (Im sin [(m+1)?ACt]) that varies with time at an integer multiple of the fundamental supply frequency. The regulator/control circuitry measures an overtone by determining the overtone's amplitude component. After generating an adjustment factor (SADJ) largely as the product of that overtone's amplitude component and an associated sinusoidal function, the regulator/control circuitry adjusts the input supply current or its rectified form by an amount corresponding to the adjustment factor for each measured overtone.
    Type: Grant
    Filed: April 6, 2007
    Date of Patent: May 18, 2010
    Inventor: Robert S. Wrathall