Abstract: The sequence in which the voltages (VSL, VDL, VSG, and VCL) applied to the source/drain regions (S and D), select gate (SG), and (if present) control gate (CG) of a floating-gate field-effect transistor (20) start to change value during a programming operation is controlled so as to avoid adjusting the transistor's programmable threshold voltage toward a programmed value when the transistor is intended to remain in the erased condition, i.e., not go into the programmed condition. With the voltage (VSL) at one source/drain region (S) changing from a nominal value to a programming value, the sequence entails causing the voltage (SG) at the select gate to start changing from a nominal value to a programming-enable value after the voltage at the other source/drain region (D) starts changing from a nominal value to a programming-inhibit value.

Abstract: An electronic memory, typically a flash EPROM, contains an array of memory sections (40), each containing an array of memory cells (54). Global bit lines (60) fully traverse the memory. Local bit lines (58) partially traverse the memory. Data stored in the memory is sensed with an arrangement that utilizes impedance matching to achieve high sensing accuracy with low noise sensitivity. The impedance matching may be provided solely from the sections and lines of the memory or partially from a separate reference memory section (102) that contains reference memory cells (104).

Abstract: A flat-panel display is fabricated by a process in which a spacer (24) having a rough face (54 or 56) is positioned between a pair of plate structure (20 and 22). When electrons strike the spacer, the roughness in the spacer's face causes the number of secondary electrons that escape the spacer to be reduced, thereby alleviating positive charge buildup on the spacer. As a result, the image produced by the display is improved. The spacer facial roughness can be achieved in various ways such as providing suitable depressions (60, 62, 64, 66, 70, 74, or 80) or/and protuberances (82, 84, 88, and 92) along the spacer's face.

Abstract: A semiconductor junction varactor utilizes gate enhancement for enabling the varactor to achieve a high ratio of maximum capacitance to minimum capacitance. The varactor has a gate region (131 or 181) divided into multiple portions of differing zero-point threshold voltages for enabling the varactor capacitance to vary relatively gradually with a control voltage applied to the varactor.

Abstract: A semiconductor junction varactor is designed with gate enhancement for enabling the varactor to achieve a high ratio of maximum capacitance to minimum capacitance. The varactor has a gate region (131 or 181) divided into multiple portions of differing zero-point threshold voltages for enabling the varactor capacitance to vary relatively gradually with a control voltage applied to the varactor.

Abstract: A spatial light modulator contains a substrate (90), a plurality of overlying liquid-crystal cells (202), a plurality of respectively corresponding transistors (204), an electron-beam system (400 and 500), and a control component (203). Each transistor is in electrical communication with the corresponding liquid-crystal cell. The electron-beam system bombards each transistor with electrons that cause it to be selectively in (i) a non-conductive condition in which its channel-region electric field is substantially insufficient for conduction or (ii) a conductive condition in which its channel-region electric field is sufficient for at least partial conduction. During selected time periods when a transistor is in its conductive condition, the control component provides the transistor with a control signal that results in the polarization direction of specified light being selectively rotated in passing through the corresponding liquid-crystal cell.

Abstract: A display (50) with enhanced image contrast contains an image-producing component (60) and a set of shutter strips (80). The image-producing component, typically a flat-panel device, has multiple imaging lines that provide light to produce an image. Each shutter strip is situated in front of one or more associated imaging lines. By appropriately switching the shutter strips between light-absorptive and light-transmissive states, the image contrast is enhanced. The shutter strips are typically implemented with a liquid-crystal display structure. The switching of the shutter strips is typically performed with a control component (52/76) which utilizes light to control the shutter switching and which is synchronized to signals (90 or/and 100) that control the imaging lines.

Abstract: A detector system for high-speed Ethernet LAN is described. One embodiment includes a detector system having N one dimensional sequence detector equalizers in combination with an N-dimensional traceback decoder. The detector system detects N-dimensional symbols transmitted over N separate transport channels to N one-dimensional receivers. In one embodiment, Gigabit Ethernet receiver includes a four-wire transport to four 1D receivers and a 4D detector. The 4D detector in one embodiment is a parity code detector. In another embodiment, the 4D detector is a 4D trellis code detector.

Abstract: A light-emitting device (52) suitable for a flat-panel cathode-ray tube display contains a light-emissive region (66) formed over a plate (64). The light-emissive region contains a plurality of light-emissive particles (72). Part of the outer surface of each of a group of the light-emissive particles is conformally covered with a group of intensity-enhancement coatings (82 and 84).

Abstract: A cobalt silicide fabrication process entails first depositing a cobalt layer (120) on a silicon-containing EPROM region. A titanium layer (130) is formed over the cobalt layer by ionized physical vapor deposition (“IPVD”) to protect the cobalt layer from contaminant gases. Cobalt of the cobalt layer is reacted with silicon of the EPROM region to form a cobalt silicide layer (210) after which the titanium layer and any unreacted cobalt are removed. Use of IPVD to form the titanium layer by improves the step coverage to produce a better cobalt silicide layer.

Abstract: An operation, typically an erasure operation, is performed on a floating-gate FET (20) whose components include a body region (BR) and a control-gate electrode (CG) above a floating-gate electrode (FG). A first body voltage (VBE) at a body node (NB) is converted into a second body voltage (VBL) applied to the body region. A first control voltage (VCE) at a control node (NC) is converted into a second control voltage (VCL) applied to the control-gate electrode. The two first voltages are placed at respective conditioning values such that the two second voltages cause the FET to be in a specified condition, typically an erased condition. The two first voltages are subsequently discharged with the body and control nodes electrically connected to each other at least as the discharging begins. The two first voltages thereby begin discharging largely simultaneously. This avoids FET damage.

Abstract: A memory such as a flash EPROM contains writing circuitry (58 and 60) that adjusts how much current or/and voltage is provided to a writing conductor (92) connected to the memory cells (50) of a cell group for simultaneously writing the bits of a bit group such as a word or byte into the cells of that cell group as a function of how many of those bits are in one of a pair of opposite logic states.

Abstract: Chemical-mechanical polishing (“CMP”) processes performed on bodies (10), each having areas (16 and 18) of different depression pattern densities, are compared by correlating polishing data accumulated, for one such body, on an area (16) of one pattern density to polishing data accumulated, for that body, on an area of another pattern density for each of the CMP processes.

Abstract: A copper-containing layer suitable for an electrical interconnect in a device such as an integrated circuit is created by a procedure in which a trench (104) is formed through a dielectric layer (102) down to a substrate (100). A diffusion barrier (106) is provided over the dielectric layer and into the trench. Copper (108) is deposited over the diffusion barrier and into the trench. Chemical mechanical polishing is utilized to remove the copper outside the trench down substantially to the diffusion-barrier material overlying the dielectric layer. A sputter etch, typically of the reactive type, is then performed to substantially remove the diffusion-barrier material overlying the dielectric layer. The sputter etch typically removes copper above and/or in the trench at approximately the same rate as the diffusion-barrier material so as to substantially avoid the undesirable dishing phenomenon.

Abstract: A flat-panel cathode-ray tube display contains electron-emissive regions (54) spaced non-uniformly apart from one another in a line of the electron-emissive regions so as to better utilize the space where the electron-emissive regions are located. Alternatively or additionally, electron focusing can be appropriately made more concentrated by implementing each electron-emissive region as two or more portions 54A-54F) situated suitably with respect to openings (86A-86F) in an electron-focusing system (76).

Abstract: Inert gas provided at a suitable level inside a hermetically sealed cathode-ray tube display, typically of the flat-panel type, enables the display's electron-emitting device (20) to be automatically cleaned during display operation subsequent to final display sealing. Upon being struck by electrons emitted by the electron-emitting device, atoms (68) of the inert gas ionize to produce positively charged ions (124) which travel backward to the electron-emitting device and dislodge overlying contaminant material (130 and 132). A getter (26) collects dislodged contaminant. A reservoir (28) provides inert gas to replace inert gas lost during the cleaning process.

Abstract: A light-emitting device (52) suitable for a flat-panel cathode-ray tube display contains a light-emissive region (66) formed over a plate (64). The light-emissive region contains a plurality of light-emissive particles (72). Part of the outer surface of each light-emissive particle is conformally covered with a coating (74) that provides light reflection or/and gettering.

Abstract: An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 &mgr;m deep into the body material but not more than 0.1 &mgr;m deep into the body material. The source/drain zones (140 and 142 or 160 and 162) of a p-channel IGFET (120 or 122) are provided with graded-junction characteristics to reduce junction capacitance, thereby increasing switching speed.

Abstract: An interconnect for a substructure having an opening (470) with a rounded perimetrical top edge (480) includes a titanium nitride layer (150) and a tungsten layer (160). The titanium layer overlies the substructure, extends into the opening, has a substantially columnar grain structure, and is less than 30 nm thick. The tungsten layer overlies/contacts the titanium nitride layer and extends into the opening. A titanium layer (140) normally no more than 36 nm thick is typically situated between the substructure and the titanium nitride layer.

Abstract: An electron-emitting device (20, 70, 80, or 90) contains an electrode, either a control electrode (38) or an emitter electrode (32), having a specified portion situated off to the side of the bulk of the electrode. For a control electrode, the specified portion is an exposure portion (38EA or 38EB) having openings that expose electron-emissive elements (50A or 50B) situated over an emitter electrode. For an emitter electrode, the specified portion is an emitter-coupling portion situated below at least one electron-emissive element exposed through at least one opening in a control electrode. Configuring the device in this way enables the control-electrode-to-emitter-electrode capacitance to be quite small, thereby enhancing the device's switching speed. If the specified portion of the electrode becomes short circuited to the other electrode, the short-circuit defect can be removed by severing the specified portion from the remainder of its electrode.