Patents Represented by Attorney, Agent or Law Firm Ronald J. Meetin
  • Patent number: 6734608
    Abstract: A structure suitable for partial or full use in a spacer (24) of a flat-panel display has a porous face (54). The structure may be formed with multiple aggregates (100) of coated particles (102) bonded together in an open manner to form pores (58). A coating (88) consisting primarily of carbon and having a highly uniform thickness may extend into pores of a porous body (46). The coating can be created by removing non-carbon material from carbon-containing species provided along the pores. A solid porous film (82) whose thickness is normally no more than 20 &mgr;m has a resistivity of 108-1014 ohm-cm. A spacer for a flat-panel display contains a support body (80) and an overlying, normally porous, layer (82) whose resistivity is greater parallel to a face of the support body than perpendicular to the body's face.
    Type: Grant
    Filed: January 25, 2001
    Date of Patent: May 11, 2004
    Assignees: Candescent Technologies Corporation, Candescent Intellectual Property Services, Inc., Nanopore Incorporated
    Inventors: Roger W. Barton, Michael J. Nystrom, Bob L. Mackey, Lawrence S. Pan, Shiyou Pei, Stephen Wallace, Douglas M. Smith
  • Patent number: 6722937
    Abstract: A flat-panel display is hermetically sealed by a process in which a first plate structure (30) is positioned generally opposite a second plate structure (32) such that sealing material (34) provided over the second plate structure lies between the plate structures. In a gravitational sealing technique, the first plate structure is positioned vertically below the second plate structure. The sealing material is heated so that it moves vertically downward under gravitational influence to meet the first plate structure and seal the plate structures together. In a global-heating gap-jumping technique, the plate structures and sealing material are globally heated to cause the sealing material to jump a gap between the sealing material and the first plate structure. When the first plate structure is positioned vertically above the second plate structure, the sealing material moves vertically upward to meet the first plate structure and close the gap.
    Type: Grant
    Filed: July 31, 2000
    Date of Patent: April 20, 2004
    Assignees: Candescent Technologies Corporation, Candescent Intellectual Property Services, Inc., Sony Corporation
    Inventors: Paul N. Ludwig, Theodore S. Fahlen, Shinji Kanagawa, Jennifer Y. Sun
  • Patent number: 6691404
    Abstract: A flat-panel display is fabricated according to a process in which a liquid-containing film (92, 116, 124, 132, 144, or 166) is formed over a substrate (80). In addition to suitable liquid, the liquid-containing film contains oxide or/and hydroxide. Liquid is removed from the liquid-containing film to convert it into a solid porous film (82 or 150) having (a) a porosity of at least 10% along an exposed face of the film, (b) an average resistivity of 108-1014 ohm-cm at 25° C., and (c) an average thickness of no more than 20 &mgr;m. A spacer (24) formed with at least a segment of the substrate and overlying solid porous film is positioned between opposing first and second plate structures (20 and 22) of the display. The second plate structure (22) emits light upon receiving electrons emitted by the first plate structure (20).
    Type: Grant
    Filed: January 25, 2001
    Date of Patent: February 17, 2004
    Assignees: Candescent Intellectual Property Services, Inc., Candescent Technologies Corporation, NanoPore Inc.
    Inventors: Roger W. Barton, Michael J. Nystrom, Bob L. Mackey, Lawrence S. Pan, Shiyou Pei, Stephen Wallace, Douglas M. Smith
  • Patent number: 6670267
    Abstract: A tungsten-based interconnect is created by first providing a structure with an opening (464/470) in a structure and then rounding the top edge of the opening. A titanium nitride layer (150) is physically vapor deposited to a thickness less than 30 nm, typically less than 25 nm, over the structure and into the opening. Prior to depositing the titanium nitride layer, a titanium layer (140) may be deposited over the structure and into the opening such that the later-formed titanium nitride layer contacts the titanium layer. In either case, the titanium nitride layer is heated, typically to at least 600° C., while being exposed to nitrogen and/or a nitrogen compound. A tungsten layer (160) is subsequently chemically vapor deposited on the titanium nitride layer and into the opening.
    Type: Grant
    Filed: June 13, 2001
    Date of Patent: December 30, 2003
    Assignee: Mosel Vitelic Inc.
    Inventor: Vincent Fortin
  • Patent number: 6630786
    Abstract: A light-emitting device (42, 68, 80, 90, or 100) suitable for a flat-panel CRT display contains a plate (54), a light-emissive region (56), a light-blocking region (58), and a light-reflective layer (60 or 70). The light-emitting device achieves one or more of the following characteristics by suitably implementing the light-reflective layer or/and providing one or more layers (72, 82, 92, and 100) along the light-reflective layer: (a) reduced electron energy loss as electrons pass through the light-reflective layer, (b) gettering along the light-reflective layer, (c) reduced secondary electron emission along the light-reflective layer, (d) reduced electron backscattering along the light-reflective layer, and (e) reduced chemical reactivity along the light-reflective layer.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: October 7, 2003
    Assignees: Candescent Technologies Corporation, Candescent Intellectual Property Services, Inc.
    Inventors: William J. Cummings, Lawrence S. Pan, Christopher J. Spindt, George B. Hopple, Colin D. Stanners, James C. Dunphy, Shiyou Pei, Theodore S. Fahlen
  • Patent number: 6599804
    Abstract: Short-channel threshold voltage roll-off and punchthrough in an IGFET (40 or 42) having a channel zone (64 or 84) situated in body material (50) are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 &mgr;m deep into the body material but not more than 0.4 &mgr;m deep into the body material.
    Type: Grant
    Filed: September 4, 2001
    Date of Patent: July 29, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Constantin Bulucea, Fu-Cheng Wang, Prasad Chaparala
  • Patent number: 6590265
    Abstract: A contact opening (940) is provided in a dielectric layer (720) overlaying a gate electrode (840). The contact opening and gate electrode are of substantially the same width, thus allowing for minimized area contact. A pair of process buffering regions (810) situated along the sidewalls of the gate electrode furnish additional landing area for the contact opening without exposing the sidewalls of the gate electrode.
    Type: Grant
    Filed: August 16, 2001
    Date of Patent: July 8, 2003
    Assignee: National Semiconductor Corporation
    Inventor: Michael E. Thomas
  • Patent number: 6576966
    Abstract: An asymmetric insulated-gate field-effect transistor (40) is configured in an asymmetric lightly doped drain structure that alleviates hot-carrier effects and enables the source characteristics to be decoupled from the drain characteristics. The transistor has a multi-part channel formed with an output portion (46), which adjoins the drain zone, and a more heavily doped input portion (42), which adjoins the source zone (44). The drain zone contains a main portion (52) and a more lightly doped extension (50) that meets the output channel portion. The drain extension extends at least as far below the upper semiconductor surface as the main drain portion so as to help reduce hot-carrier effects. The input channel portion is situated in a threshold body zone (53) whose doping determines the threshold voltage. The provision of a lightly doped source extension is avoided so that improving the drain characteristics does not harm the source characteristics, and vice versa.
    Type: Grant
    Filed: March 23, 2000
    Date of Patent: June 10, 2003
    Assignee: National Semiconductor Corporation
    Inventor: Constantin Bulucea
  • Patent number: 6571464
    Abstract: Methods and structures are provided which support spacer walls in a position which facilitates installation of the spacer walls between a faceplate structure and a backplate structure of a flat panel display. In one embodiment, spacer feet are formed at opposing ends of the spacer wall. These spacer feet can be formed of materials such as ceramic, glass and/or glass frit. The spacer feet support the corresponding spacer wall on the faceplate (or backplate) structure. Tacking electrodes can be provided on the faceplate (or backplate) structure to assert an electrostatic force on the spacer feet, thereby holding the spacer feet in place during installation of the spacer wall. The spacer wall can be mechanically and/or thermally expanded prior to attaching both ends of the spacer wall to the faceplate (or backplate) structure. The spacer wall is then allowed to contract, thereby introducing tension into the spacer wall which tends to straighten any inherent waviness in the spacer wall.
    Type: Grant
    Filed: April 26, 2001
    Date of Patent: June 3, 2003
    Assignees: Candescent Technologies Corporation, Candescent Intellectual Property Services, Inc.
    Inventors: Theodore S. Fahlen, Alfred S. Conte, Robert M. Duboc, Jr., George B. Hopple, John K. O'Reilly, Vasil M. Chakarov, Robert L. Marion, Steve T. Cho, Robert G. Neimeyer, Jennifer Y. Sun, David L. Morris, Christopher J. Spindt, Kollengode S. Narayanan
  • Patent number: 6566204
    Abstract: To furnish an IGFET (120 or 122) with an asymmetrically doped channel zone (144 or 164), a mask (212) is provided over a semiconductor body and an overlying electrically insulated gate electrode (148P or 168P). Ions of a semiconductor dopant species are directed toward an opening (213) in the mask from two different angular orientations along paths that originate laterally beyond opposite respective opening-defined sides of the mask. The location and shape of the opening are controlled so that largely only ions impinging from one of the angular orientations enter the intended location for the channel zone. Ions impinging from the other angular orientation are shadowed by the mask from entering the channel zone location. Although the ions impinging from this other angular orientation do not significantly dope the channel zone location, they normally enter the semiconductor body elsewhere, e.g., the intended location for the channel zone of another IGFET.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: May 20, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Fu-Cheng Wang, Constantin Bulucea
  • Patent number: 6548842
    Abstract: An IGFET (40 or 42) has a channel zone (64 or 84) situated in body material (50). Short-channel threshold voltage roll-off and punchthrough are alleviated by arranging for the net dopant concentration in the channel zone to longitudinally reach a local surface minimum at a location between the IGFET's source/drain zones (60 and 62 or 80 and 82) and by arranging for the net dopant concentration in the body material to reach a local subsurface maximum more than 0.1 &mgr;m deep into the body material but not more than 0.4 &mgr;m deep into the body material.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: April 15, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Constantin Bulucea, Fu-Cheng Wang, Prasad Chaparala
  • Patent number: 6522162
    Abstract: A test system includes (a) a tester mechanism (16 and 42) having tester contacts (152) for carrying test signals, (b) an interface module (44), and (c) a device-side board (46) having device-side contacts (162) for connection to external leads of an electronic device (40) under test. The interface module contains a tester-side body (50) having tester-side openings (86) for being positioned opposite the tester contacts, a device-side body (52) having device-side openings (136) for being positioned opposite the device-side contacts, and interface conductors (54) extending through the tester-side and device-side openings for connecting the tester contacts to the device-side contacts. The tester body is configured, typically as at least five wedge-shaped portions (68), in such a manner as to enable the electronic device under test to have an increased number of external leads.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: February 18, 2003
    Assignee: NPTest, Inc.
    Inventors: Gary W. Griffin, Myngoc T. Nguyen, Gary A. Wells, Carl R. Gore, John W. Joy, Chris A. Shmatovich
  • Patent number: 6500885
    Abstract: A liquid chemical formulation suitable for making a thin solid polycarbonate film contains polycarbonate material and a liquid typically capable of dissolving the polycarbonate material to a concentration of at least 1%. The polycarbonate material may consist of homopolycarbonate or/and copolycarbonate. Examples of the liquid include pyridine, a ring-substituted pyridine derivative, pyrrole, a ring-substituted pyrrole derivative, pyrrolidine, a pyrrolidine derativive, chlorobenzene, and cyclohexanone. A liquid film (36A) of the formulation is formed over a substructure (30) and processed to remove the liquid. The resultant solid polycarbonate film can later serve as a track layer through which charged particles (70) are passed to form charged-particle tracks (72). Apertures (74) are created through the track layer by a process that entails etching along the tracks. The aperture-containing polycarbonate track layer is typically used in fabricating a gated electron-emitting device.
    Type: Grant
    Filed: October 29, 1999
    Date of Patent: December 31, 2002
    Assignees: Candescent Technologies Corporation, Candescent Intellectual Property Services, Inc.
    Inventors: John D. Porter, Michael P. Skinner, Stephanie Simmons
  • Patent number: 6489718
    Abstract: A spacer (140) suitable for use in a flat panel display is formed with ceramic, transition metal, and oxygen. At least part of the oxygen is bonded to the transition metal or/and constituents of the ceramic to form a uniform electrically resistive material having a resistivity of 105-1010 ohm-cm and a secondary electron emission coefficient of less than 2 at 2 kilovolts.
    Type: Grant
    Filed: July 18, 2000
    Date of Patent: December 3, 2002
    Assignees: Candescent Technologies Corporation, Candescent Intellectual Property Services, Inc.
    Inventors: Anthony P. Schmid, Christopher J. Spindt, David L. Morris, Theodore S. Fahlen, Yu Nan Sun
  • Patent number: 6461932
    Abstract: A trenched-isolated semiconductor structure is created by a process that entails forming a patterned trench (54) along an upper surface of a semiconductor body (40). A dielectric layer (56) is provided over the upper semiconductor surface. The dielectric layer is covered with a smoothening layer (60) whose upper surface is smoother than the upper surface of the dielectric layer. The smoothening layer is removed starting from its upper surface. During the removal of the smoothening layer, upward-protruding material of the dielectric layer progressively becomes exposed and is also removed. As a result, the remainder of dielectric layer has a smoother upper surface than the initial upper surface of the dielectric layer.
    Type: Grant
    Filed: December 14, 1998
    Date of Patent: October 8, 2002
    Assignee: National Semiconductor Corporation
    Inventor: Fu-Cheng Wang
  • Patent number: 6420888
    Abstract: A module (44) for a test system interfaces between (a) a tester mechanism (16 and 42) having tester contacts (152) for carrying test signals and (b) a device-side board (46) having device-side contacts (162) for connection to external leads of an electronic device (40) under test. The interface module contains a tester side body (50) having tester side openings (86) for being positioned opposite the tester-side contacts, a device-side body (52) having device-side openings (136) for being positioned opposite the device-side openings, and interface conductors (54) extending through the tester-side and device-side openings for connecting the tester contacts to the device-side contacts. The tester body is configured, typically as at least five wedge-shaped portions (68), in such a manner as to enable the electronic device under test to have an increased number of external leads.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: July 16, 2002
    Assignee: Schlumberger Technologies, Inc.
    Inventors: Gary W. Griffin, Myngoc T. Nguyen, Gary A. Wells, Carl R. Gore, John W. Joy, Chris A. Shmatovich
  • Patent number: 6416375
    Abstract: A pair of plate structures (40 and 44), such as a baseplate structure and a faceplate structure of a flat-panel display, are sealed to each other by first attaching the plate structures to each other, typically at multiple attachment locations, in a non-vacuum environment. The plate structures are then hermetically sealed to each other, typically through an outer wall (44) or/and typically by gap jumping, in a vacuum environment.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: July 9, 2002
    Assignees: Candescent Technologies Corporation, Candescent Intellectual Property Services, Inc.
    Inventors: Steven T. Cho, Alfred S. Conte, Paul N. Ludwig, Anthony P. Schmid, Theodore S. Fahlen, Robert J. Pressley
  • Patent number: 6414428
    Abstract: The intensity at which electrons emitted by a first plate structure (10) in a flat-panel display strike a second plate structure (12) for causing it to emit light is controlled so as to reduce image degradation that could otherwise arise from undesired electron-trajectory changes caused by effects such as the presence of a spacer system (14) between the plate structures. An electron-emissive region (20) in the first plate structure typically contains multiple laterally separated electron-emissive portions (201 and 202) for selectively emitting electrons. An electron-focusing system in the first plate structure has corresponding focus openings (42P1 and 42P2) through which electrons emitted by the electron-emissive portions respectively pass. Upon being struck by the so-emitted electrons, a light-emissive region (22) in the second plate structure emits light to produce at least part of a dot of the display's image.
    Type: Grant
    Filed: April 30, 1999
    Date of Patent: July 2, 2002
    Assignees: Candescent Technologies Corporation, Candescent Intellectual Property Services, Inc.
    Inventors: Donald R. Schropp, Jr., John E. Field, James C. Dunphy, Lawrence S. Pan, David L. Morris, Ronald S. Besser, Christopher J. Spindt
  • Patent number: 6406346
    Abstract: A spacer (44) for a flat-panel display is formed with a main spacer portion (60), typically shaped like a wall, and a face electrode (66) situated over a face of main spacer portion. The spacer is inserted between two opposing plate structures (40 and 42) of the display. The face electrode causes electrons moving from one of the plate structures to the other to be deflected in such a manner as to compensate for other electron deflection caused by the presence of the spacer. The face electrode is divided into multiple laterally separated segments (661-66N) to improve the accuracy of the compensation along the length of the spacer. A masking step is typically utilized in defining the widths of the segments of the face electrode.
    Type: Grant
    Filed: May 8, 2000
    Date of Patent: June 18, 2002
    Assignees: Candescent Technologies Corporation, Candescent Intellectual Property Services, Inc.
    Inventors: Christopher J. Spindt, John E. Field
  • Patent number: 6403209
    Abstract: A structure that is suitable for partial or full use in a spacer of a flat-panel display. The structure may be formed with a porous body having a face along which multiple primary pores extend into the porous body. A coating consisting primarily of carbon and having a highly uniform thickness overlies the porous body's face, extending along the primary pores to coat their surfaces and converting the primary pores into further pores. The coating can be created by removing non-carbon material from carbon-containing species provided along the pores. A solid porous film whose thickness is normally no more than 20 &mgr;m has a resistivity of 108-1014 ohm-cm. A spacer for a flat-panel display contains a support body and an overlying, normally porous, layer whose resistivity is greater parallel to a face of the support body than perpendicular to the body's face.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: June 11, 2002
    Assignees: Candescent Technologies Corporation, Candescent Intellectual Property Services, Inc., NanoPore Incorporated
    Inventors: Roger W. Barton, Michael J. Nystrom, Bob L. Mackey, Lawrence S. Pan, Shiyou Pei, Stephen Wallace, Douglas M. Smith