Abstract: Interference rejection (85) can be applied to a wireless communication signal with reduced computational complexity by producing from a sample vector (y) a plurality of vectors (w) that are smaller than the sample vector. The interference rejection operation can then be applied to each of the smaller vectors individually to decide communication symbols represented by the sample vector.

Abstract: A transmitter using quadrature modulation includes a rectangular to polar converter for converting data symbols into a polar form, where each polar symbol has a magnitude signal and an angle signal. Digital phase modulation circuitry includes an all digital PLL circuit for generating a phase modulated RF carrier signal responsive to the angle signal frequency control word (FCW) and a carrier frequency FCW. A digitally controlled amplifier for amplifying the phase modulated signal is controlled by a digital amplitude control circuitry for controlling the gain of the digitally controlled amplifier responsive to the magnitude signal.

Abstract: Systems, methods, and storage media for accessing indirect memory in Java applications are provided. In some embodiments, a storage medium is provided that comprises Java application software that performs one or more operations on an indirect memory of a device. The software comprises instructions that create an instance of a Java class representing the indirect memory, and instructions that access a memory element of the indirect memory using an element unique identifier (“euid”) of the memory element. Other embodiments provide a method for accessing memory elements of a device that comprises creating an instance of a Java class representing the memory elements, and accessing a memory element of the memory elements using an element unique identifier (“euid”) of the memory element, wherein the memory elements are not mapped into the data memory space of the processor.

Abstract: A processing system includes a processor (20) having an idle mode node for generating an idle mode signal indicating whether the processor is in an idle mode and a memory (22) having a data retention node for receiving a data retention mode signal. The memory includes circuitry for placing the memory in a low power state responsive to the data retention mode signal. The idle mode signal drives the data retention node, such that the memory is placed in the low power state when the processor is in idle mode.

Abstract: A transmitter comprising circuitry (14) for converting input bits to a plurality of symbols; and circuitry (24x) for forming a complex conjugate of signals corresponding to selected ones of the plurality of symbols. The selected ones of the plurality of symbols consist of signals corresponding to some and less than all the plurality of symbols. The transmitter also comprises circuitry (28x) for space time encoding both the signals corresponding to the selected ones of the plurality of symbols and signals corresponding to non-selected ones of the plurality of symbols. Lastly, the transmitter comprises a plurality of transmit antennas (TATx) coupled to transmit signals in response to the circuitry for space time encoding.

Abstract: Embodiments of the present disclosure provide a power-optimizing memory analyzer, a method of operating a power-optimizing memory analyzer and a memory system employing the analyzer or the method. In one embodiment, the power-optimizing memory analyzer is for use with an array of memory blocks and includes a task database configured to provide a parameter set corresponding to each of a set of tasks to be performed in a system. The power-optimizing memory analyzer also includes an allocation module configured to determine offline, a group of memory blocks in the array corresponding to the parameter set for each task and based on providing a power reduction for the array. The power-optimizing memory analyzer further includes a power profiling module configured to generate run-time power profiles of memory power states for each task allowing transparent and dynamic control of the memory power states while maintaining a required quality of service.

Abstract: A novel and useful apparatus for and method of Bluetooth and WiMAX coexistence. The invention provides a system approach to achieving coexistence between Bluetooth and WiMAX transceivers collocated in a mobile terminal. The coexistence mechanism of the present invention is particularly suited to operation of WiMAX in the 2.3 GHz and 2.5 GHz frequency bands. In operation, the coexistence mechanism of the present invention utilizes multiple algorithms depending on the capabilities of the Bluetooth peer and the power save support level of the WiMAX base station. In the example embodiment presented herein, the coexistence mechanism is implemented in the MAC layer of the Bluetooth and WiMAX radio modules.

Abstract: A novel and useful apparatus for and method of improving idle connection state power consumption in wireless local area network (WLAN) system. Beacon transmission delay information is determined by the access points and advertised to the stations via a Beacon Transmission Delay Information Element. In response, the stations adjust their Wake For Beacon Reception time accordingly to wake up at a time much closer to the actual receipt of the Beacon, thereby reducing power consumption due to the reduced time the receive circuits need to be powered on.

Abstract: A method of operating a phase locked loop (FIG. 5) for a wireless receiver is disclosed. The method includes receiving a reference signal (503) having a first and a second plurality of cycles and receiving a feedback signal (512) having the first and the second plurality of cycles. The feedback signal is compared (504) to the reference signal. A plurality of phase errors is produced for each cycle of (UP, FIG. 10A) the first plurality of cycles in response to the step of comparing.

Abstract: In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defeats are within an allowable range.

Abstract: The present invention pertains to a method of calibrating reception properties of a radio frequency (RF) processor. The application describes two embodiments of the invention representing calibration of the properties using an auxiliary transmitter to generate a calibration signal internal to the RF processor.

Abstract: A modulation circuit uses pre-calculated and stored data to generate the modulated output. The modulator architecture uses pre-calculated, Gaussian filtered sine and cosine responses that are stored in a ROM (read-only memory) or other memory structure. The modulator output is then calculated as a simple sum of values read from the ROM and controlled by the input burst data stream.

Abstract: A circuit and method for providing a fully integrated DC-DC converter using on-chip switched capacitors is disclosed. A switched capacitor matrix is coupled as a digitally controlled transfer capacitor. A pair of non-overlapping, fixed frequency clock signals is provided to a switched capacitor circuit including the switched capacitor matrix and a load capacitor coupled to the output terminal. A DC input voltage supply is provided. A hysteretic feedback loop is used to control the voltage at the output as a stepped-down voltage from the input by digitally modulating the transfer capacitor using switches in the switch matrix to couple more, or fewer, transfer capacitors to the output terminal during a clock cycle. A coarse and a fine adjustment circuit are provided to improve the regulation during rapid changes in load power. A method of operating the regulator is disclosed.

Abstract: A multi-tap direct sub-sampling mixing system for wireless receivers is provided with a dynamically configurable passive switched capacitor filter. A front end amplifier is connected to receive a signal. The passive switched capacitor filter is connected to receive the amplified signal and has an output for providing a filtered signal. The switched capacitor filter has at least two sections that are each operable as a pole, wherein a first section of the at least two sections has sets of at least two stacked capacitors interconnected with a set of switches operable to amplify in input voltage provided to an input of the first section in response to operation of the set of switches; and a back end section connected to the output of the switched capacitor filter to receive the filtered signal.

Abstract: A Global Navigation Satellite System (GNSS) receiver provided according to an aspect of the present invention contains a buffer to store less than a number of samples spanning a code period of a received GNSS signal, with the samples being used by a correlator and a processor to perform various searches in the receiver. Due to the use of such smaller memory space in the buffer, the overall size of receivers may be reduced. According to another aspect of the present invention, the amount of storage provided for storing local code and carrier samples (used during correlation) is also reduced by dynamically generating the local code and carrier sample as required for generating partial correlation results.

Abstract: A current canceling CMOS variable gain amplifier includes a first leg and a second leg. The first leg has a first input line, a first output line, a first ON transistor, a first control transistor and a first subtracting transistor. The second leg has a second input line, a second output line, a second ON transistor, a second control transistor and a second subtracting transistor. The second input line can provide a second input current. The second output line can provide a second output current. The first input line is arranged to provide a first input current to each of the first ON transistor, the first control transistor and the first subtracting transistor. The second input line is arranged to provide a second input current to each of the second ON transistor, the second control transistor and the second subtracting transistor. The first output line is in electrical connection with each of the first ON transistor, the first control transistor and the second subtracting transistor.

Abstract: An output buffer provided according to an aspect of the present invention is designed to generate an output signal with a slew rate that is substantially independent of the threshold voltage of transistors contained within. An output buffer provided according to another aspect of the present invention provides output signals with different slew rates depending on the magnitude of the load capacitance at the output node of the output buffer.

Abstract: One embodiment of the invention includes a mixed-signal filter. The mixed-signal filter comprises an analog signal path configured to process a first analog signal and an analog-to-digital converter (ADC) configured to convert the processed first analog signal to a digital signal. The mixed-signal filter also comprises a programmable digital feedback filter configured to filter the digital signal and a digital-to-analog converter (DAC) configured to convert the filtered digital signal to a second analog signal. The mixed-signal filter further comprises a signal combiner configured to combine an analog input signal of the mixed-signal filter and the second analog signal to generate the first analog signal.

Abstract: Embodiments of the invention provide methods for optimizing the spectral efficiency of control channel transmissions carrying scheduling assignments from a serving Node B to user equipments. This is accomplished through the selection of the modulation and coding scheme with the highest spectral efficiency that can support transmission of a scheduling assignment to the corresponding user equipment with a reception performance satisfying a target error rate.

Abstract: Systems and methods for a multi-sharing security firewall are provided. Embodiments of a memory security firewall apparatus are provided that include region configuration logic, region selection logic, and access validation logic. The region configuration logic is operable to define memory protection regions of a target memory, each memory protection region having two initiator groups and two sets of access attribute combinations, one for each initiator group. The region selection logic is operable to select a memory protection region that includes the address of a target memory access request from a system initiator. The access validation logic is operable to allow the requested memory access if the system initiator is in one of the initiator groups of the memory protection region selected by the region selection logic, and the combination of access attributes is in a set of access attribute combinations of the memory protection region.