Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. A synthesizer provides 4/3 the desired frequency fRF. This frequency is divided by two to obtain in-phase and quadrature square waves at ? fRF. The in-phase signal is divided by two again to obtain in-phase and quadrature square waves at ? fRF. The signals are then logically combined using XOR operations to obtain I and Q branch signals containing spectral spurs. Since the spurs are located in non-disturbing bands, they can be filtered out resulting in the desired output signal.

Abstract: A filter circuit includes a differential amplifier circuit to provide a number of poles including a dominant pole, and a feedback circuit to feed a portion of an output of the differential amplifier circuit to an input of the differential amplifier circuit. The feedback circuit includes a feedback resistor and a feedback capacitor to provide a controllable increase in an order of a transfer function of the filter circuit along with non-dominant poles of the differential amplifier circuit coupled in parallel with the feedback resistor. Coefficients of a transfer function of the differential amplifier circuit are forced to substantially depend solely on one or more of a plurality of passive circuit elements, the feedback resistor, and the feedback capacitor to control a dependence of the transfer function of the filter circuit on a gain of the differential amplifier circuit and poles of the differential amplifier circuit.

Abstract: A computing platform (10) protects system firmware (30) using a manufacturer certificate (36). The manufacturer certificate binds the system firmware (30) to the particular computing platform (10). The manufacturer certificate also stores configuration parameters and device identification numbers. A secure run-time platform data checker (200) and a secure run-time checker (202) check the system firmware during operation of the computing platform (10) to ensure that the system firmware (30) or information in the manufacturer certificate (36) has not been altered. Application software files (32) and data files (34) are bound to the particular computing device (10) by a platform certificate (38). Configuration parameters may be stored in a data file (34) with an associated platform certificate (38).

Abstract: A receiver to recover a signal of interest while consuming reduced power in some scenarios. The receiver contains a in-phase channel processing path and a quadrature phase channeling path for down converting an input signal to an intermediate frequency, and then recovering the signal of interest by further processing of the input signal at intermediate frequency. One of the two paths is turned off upon occurrence of a desired condition, which reduces power consumption. In an embodiment, the condition is that the input signal does not contain an image signal of the signal of interest.

Abstract: A wireless communication system (10). The system comprises transmitter circuitry (BST1) comprising circuitry for transmitting a plurality of frames to a receiver in a first cell (Cell 1). Each of the plurality of frames comprises a bit group (22), and the bit group uniquely distinguishes the first cell from a second cell (Cell 2) adjacent the first cell. The transmitter circuitry further comprises circuitry (54) for inserting a bit sequence into the bit group. The bit sequence is selected from a plurality of bit sequences (S1-SK) such that successive transmissions by the transmitter circuitry comprise a cycle of successive ones of the plurality of bit sequences.

Abstract: A mobile communication system is designed with an input circuit coupled to receive a first plurality of signals (rj(i+?j), i=0?N?1) during a first time (T0-T1) from an external source and coupled to receive a second plurality of signals (rj (i+?j), i=N?2N?1) during a second time (T1-T2) from the external source. The input circuit receives each of the first and second plurality of signals along respective first and second paths (j). The input circuit produces a first input signal (Rj1) and a second input signal (Rj2) from the respective first and second plurality of signals. A correction circuit is coupled to receive a first estimate signal (?j1), a second estimate signal (?j2) and the first and second input signals. The correction circuit produces a first symbol estimate ({tilde over (S)}1) in response to the first and second estimate signals and the first and second input signals.

Abstract: Apparatus and methods for accessing a wireless telecommunications network by transmitting a random access signal. The random access signal includes a random access preamble signal selected from a set of random access preamble signals constructed by cyclically shift selected root CAZAC sequences. The random access signal may be one or more transmission sub-frames in duration, the included random access preamble sequence's length being extended with the signal to provide improved signal detection performance in larger cells and in higher interference environments. The random access signal may include a wide-band pilot signal facilitating base station estimation of up-link frequency response in some situations. Each of the plurality of available random access preamble sequences may be assigned a unique information value. The base station may use the information encoded in the random access preamble to prioritize responses and resource allocations.

Abstract: A fast locking delay-locked loop (DLL), which can also operate as a clock data recovery circuit (CDR), includes a delay chain, a sampling circuit and a transition detector. An input signal and delayed versions of the input signal generated by the delay chain are sampled by the sampling circuit. The outputs of the sampling circuit are provided to a transition detector which selects one of the input signal and its delayed versions determined to have signal transitions most closely aligned with a sampling edge of a clock. The selected signal and the clock are provided as inputs to a phase discriminator which generates an error signal representing a level of phase mismatch between the inputs. The error signal is fed back to the sampling circuit to maintain phase lock between the clock signal and the input bit stream.

Abstract: A system comprising an imaging device adapted to capture images of a target object at multiple angles. The system also comprises storage coupled to the imaging device and adapted to store a generic model of the target object. The system further comprises processing logic coupled to the imaging device and adapted to perform an iterative process by which the generic model is modified in accordance with the target object. During each iteration of the iterative process, the processing logic obtains structural and textural information associated with at least one of the captured images and modifies the generic model with the structural and textural information. The processing logic displays the generic model.

Abstract: A transmission of information from a secondary to a primary node occurs in a plurality of N logical time durations. The transmission from the secondary to primary node in a wireless network is obtained using a first and a second sequence. Embodiments of the present invention mitigate interference by restricting the choice of the first sequence. Thus, in an embodiment of the invention, the first sequence is selected from a set of M sequences wherein M is strictly less than N. In order to accommodate high-velocity users, the restricted set contains a pair of sequences whose element-wise product is mirror symmetric. A transmission component for K-th logical time duration is obtained from the entire second sequence and K-th element of the first sequence.

Abstract: Various apparatuses and methods for protecting a transmitter from electrostatic discharge are disclosed herein. For example, some embodiments provide an apparatus including a first ESD clamp connected to an antenna input, a first reactive component connected to the first ESD clamp, a second ESD clamp connected to the first reactive component, and a second reactive component connected between the second ESD clamp and the transmitter.

Abstract: A circuit for aligning input signals includes a clock generating circuit (CGC) responsive to first signal and second signal to generate a clock signal. A first flip flop and a second flip flop, coupled to the CGC, are responsive to first type of edge of the clock signal to output the first signal and the second signal. A finite state machine (FSM), coupled to the CGC, the first flip flop and the second flip flop, is responsive to second type of edge of the clock signal to detect early arrival of one of the first signal and the second signal with respect to each other, and to generate first control signal and second control signal. A first programmable delay element and a second programmable delay element, coupled to the FSM, delays first input signal based on the first control signal and second input signal based on the second control signal.

Abstract: Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter includes a synchronization unit configured to provide a primary synchronization signal and a secondary synchronization signal having first and second segments. The transmitter also includes a secondary scrambling unit configured to provide a scrambled secondary synchronization signal, wherein scrambling agents for the first and second segments are derived from a primary synchronization sequence of the primary synchronization signal. The secondary scrambling unit is further configured to provide an additional scrambling of one of the first and second segments, wherein a second scrambling agent is derived from the remaining segment of a secondary synchronization sequence of the secondary synchronization signal.

Abstract: The present invention exploits the benefits obtainable from using transmit diversity by designing the size of the interleaver matrix to avoid the case where most or all of the bits in a row are transmitted on a single antenna (110 or 112). This can be accomplished, for example, by specifying the interleaver matrix based on the type of modulation (308) used. A symbol scrambler can also be used to exploit the benefits obtainable from using transmit diversity.

Abstract: A synchronous circuit for clock multiplexing and output-enable is implemented using a pair of logic gates and an output block. Select signals and enable signals with the corresponding logic sense are provided as inputs to the pair of logic gates, which generate respective logic outputs. The output block contains synchronizers clocked by respective input signals, and receives the logic outputs also as inputs. The output block provides a selected one of the input signals as an output, the provision of the selected input signal being accomplished in a synchronous fashion. Enabling and disabling of the output are also performed synchronously.

Abstract: Symbols are transmitted in a Cartesian transmitter by pre-distorting an input signal X having in-phase and quadrature components using a first compensation lookup table operable to hold complex valued entries to carry out in-phase and quadrature compensation pre-distortion with respect to the input signal to form a pre-distorted signal Z. The pre-distorted signal Z is processed to form an output signal Y using a nonlinear element. A complex gain normalization parameter adaptively updated to reflect varying gain of a linear region of the nonlinear element. A normalized feed back signal {tilde over (Y)} is formed using the adaptively updated complex gain normalization parameter. The first compensation lookup table is updated based on the pre-distorted input signal Z and the adaptively normalized feedback signal {tilde over (Y)}.

Abstract: A predistorters for use with a nonlinear element and methods of predistorting for a nonlinear element for use in a 3G, e.g., WCDMA transmitter. In one embodiment, the predistorter includes: (1) a lookup table having non-uniformly spaced entries therein, (2) a compander configured to compand an input signal based on a nonlinearity of the nonlinear element to address the entries and (3) an interpolation offset calculation circuit associated with the lookup table and configured to produce an output based on a value of the input signal and a linear interpolation involving at least two entries from the lookup table.

Abstract: A novel and useful apparatus for and method of nonlinear adaptive phase domain equalization for multilevel phase coded demodulators. The invention improves the immunity of phase-modulated signals (PSK) to intersymbol interference (ISI) such as caused by transmitter or receiver impairments, frequency selective channel response filtering, timing offset or carrier frequency offset. The invention uses phase domain signals (r, ?) rather than the classical Cartesian quadrature components (I, Q) and employs a nonlinear adaptive equalizer on the phase domain signal. This results in significantly improved ISI performance which simplifies the design of a digital receiver.

Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal with a plurality of phases. A switch is coupled to receive the RF clock, and is operative to select one of the plurality of phases. A phase detection circuit is coupled to the switch and is operable to receive a selected phase and to provide digital phase error samples indicative of a time difference between the reference clock and the selected phase.

Abstract: A circuit is designed with a measurement circuit (432). The measurement circuit is coupled to receive a first input signal (903) from a first antenna (128) of a transmitter and coupled to receive a second input signal (913) from a second antenna (130) of the transmitter. Each of the first and second signals is transmitted at a first time. The measurement circuit produces an output signal corresponding to a magnitude of the first and second signals. A control circuit (430) is coupled to receive the output signal and a reference signal. The control circuit is arranged to produce a control signal at a second time in response to a comparison of the output signal and the reference signal.