Abstract: A digital camera function, such as can be implemented in a cellular telephone handset, and that includes automated segmentation of foreground subjects in acquired digital photos and images. Successive images are captured by the digital camera function at different flash exposure levels, for example using existing light only and using flash exposure. After alignment and registration of the images, luminance difference values in the two images are determined for each pixel, and the luminance difference values compared against a threshold value on a pixel-by-pixel basis. Those pixels with luminance difference values exceeding the threshold are segmented from the image as foreground subjects.

Abstract: Apparatus and method for providing correlation in a CDMA receiver. A Generic Correlation Coprocessor comprises one or more correlation blocks. Each correlation block comprises a correlation input buffer coupled to one or more correlators. The correlators are coupled to an interpolator input buffer and to a correlator output buffer. One or more interpolators are coupled to the interpolation input buffer and to the correlation output buffer. The correlators correlate the received signal with PN codes to produce a correlated signal. The correlated signal is stored in the correlator output buffer and/or the interpolation input buffer, and provided from the interpolation input buffer to the one or more interpolators. The one or more interpolators interpolate the correlated signal to produce an interpolated signal. The interpolated signal is stored in the correlator output buffer. Signals are provided from the correlator output buffer to other receiver processing systems.

Abstract: Predistortion methods and apparatus for transmitter linearization in a communication transceiver are disclosed.

Abstract: A method of operating a phase locked loop (FIG. 5) for a wireless receiver is disclosed. The method includes receiving a reference signal (503) having a first and a second plurality of cycles and receiving a feedback signal (512) having the first and the second plurality of cycles. The feedback signal is compared (504) to the reference signal. A plurality of phase errors is produced for each cycle of (UP, FIG. 10A) the first plurality of cycles in response to the step of comparing.

Abstract: Embodiments of the invention provide a method to efficiently enable Network MIMO for use in the downlink direction. An association is established between a primary NodeB in a first cell and a secondary NodeB in an adjacent second cell. A set of downlink transmission resources is reserved for use by both the primary NodeB and the secondary NodeB. A transport block is transmitted from the secondary NodeB simultaneously with the primary NodeB to a user equipment (UE) near the edge of the first cell in response to a schedule provided by the primary NodeB. A time instance of the reserved transmission resources is released by the secondary NodeB when no simultaneous transmission of a transport block is scheduled within a minimum time.

Abstract: A time to digital converter is used to determine which edge of the higher frequency clock (oversampling clock) is farther away from the edge of the lower frequency timing signal. At the same time, the oversampling clock performs sampling of the timing signal by two registers: one on the rising edge and the other on the falling edge. Then, the register of “better quality” retiming, as determined by the fractional phase detector decision, is selected to provide the retimed output.

Abstract: Apparatus and method for employing a Hardware Processing Function in a processor system using a hierarchical memory. Embodiments of the disclosed invention may be used to enhance processor performance and functionality while maintaining cache coherency and reducing cache pollution. A system includes a processor, a hierarchical memory system coupled to the processor, and a Hardware Processing Function coupled to the hierarchical memory system. The processor is configured to decode an instruction and the hierarchical memory system is configured to execute the instruction. The instruction directs the memory system to perform a data manipulation. The processor transfers a value to the memory system. The value comprises a location of source data to be manipulated, a selection of a Hardware Processing Function to perform the data manipulation, and a destination storage location where the manipulated data is to be stored.

Abstract: Oscillator circuit for radio frequency transceivers. An oscillator circuit includes a first oscillator that generates a signal having a first frequency and a second oscillator that generates a signal having a second frequency. The oscillator circuit includes a mixer that is responsive to the signal having the first frequency and the signal having the second frequency to provide a signal having a third frequency and one or more frequency components. The oscillator circuit includes a filter that is responsive to the signal from the mixer to attenuate the one or more frequency components and provide a signal having a desired frequency. The oscillator circuit includes a correction circuit to correct a drift in at least one of the first frequency and the second frequency by controlling the second frequency, thereby correcting the drift in the third frequency and the desired frequency.

Abstract: A wireless communication system. The system comprises transmitter circuitry (BST1), the transmitter circuitry comprising encoder circuitry (50) for transmitting a plurality of frames (FR). Each of the plurality of frames comprises a primary synchronization code (PCS) and a secondary synchronization code (SSC). The encoder circuitry comprises of circuitry (501) for providing the primary synchronization code in response to a first sequence (32). The encoder circuitry further comprises circuitry (502) for providing the secondary synchronization code in response to a second sequence (54) and a third sequence (56). The second sequence is selected from a plurality of sequences. Each of the plurality of sequences is orthogonal with respect to all other sequences in the plurality of sequences. The third sequence comprises a subset of bits from the first sequence.

Abstract: Closed loop multiple-antenna wireless communications system with antenna weights determined by maximizing a composite channel signal-to-interference-plus-noise ratio minimum. Multiplexed symbol streams over subsets of antennas enhance throughout.

Abstract: A novel and useful self-calibration based production line testing mechanism utilizing built-in closed loop measurements in the radio to calibrate the output power of an external power amplifier coupled to a SoC radio. The mechanism is applicable during production line testing and calibration which is performed on each SoC and associated external power amplifier after assembly at the target PCB of the final product. The mechanism calibrates the TX output power in three phases based on loopback EVM measurements. In a first phase, the PPA in the radio (SoC) is calibrated and gain versus output power is stored in a gain table in on-chip NVS. In a second phase, the maximum PPA TX power is determined using closed loop EVM measurements. The external PA is calibrated in a third phase and the maximum PA power is determined. During this third phase, the maximum power of the device is calculated, compared to the requirements of the particular standard and a pass/fail determination is thereby made.

Abstract: A reconfigurable chip level equalizer having circuitry that restores signal orthogonality and eliminates channel interference for a wireless transmitted signal. In at least some embodiments, the reconfigurable chip level equalizer comprises two or more adaptive equalizers, a plurality of operational blocks that interconnect the two or more adaptive equalizers, and a control mechanism that configures the two or more adaptive equalizers and operational blocks according to different signal delay profiles.

Abstract: The present invention provides a method of operating a base station transmitter. In one embodiment, the method includes providing a cellular downlink synchronization signal having primary and secondary portions, wherein the primary portion is common for all cells and the secondary portion is cell-specific and transmitting the cellular downlink synchronization signal. In another embodiment, the method includes providing a cellular downlink synchronization signal having primary and secondary portions wherein the primary portion employs a corresponding one of a plurality of different primary signals allocated to adjoining transmission cells. The method also includes further providing cell-specific information in the secondary portion and transmitting the cellular downlink synchronization signal. The present invention also provides a method of operating user equipment.

Abstract: A novel and useful apparatus for and method of spur reduction using computation spreading with dithering in a digital phase locked loop (DPLL) architecture. A software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU is adapted to spread the computation of the atomic operations out over a PLL reference clock period wherein each computation is performed at a much higher processor clock frequency than the PLL reference clock rate. This significantly reduces the per cycle current transient generated by the computations. The frequency content of the current transients is at the higher processor clock frequency which results in a significant reduction in spurs within sensitive portions of the output spectrum.

Abstract: A method for tuning a transmitter in order to improve impedance matching to an antenna or to intermediate radio frequency stages uses an error detector that senses a deviation of the amplitude or phase angle of a load current of a power amplifier driver or of a power amplifier. A controller calculates a correction and dynamically adjusts tunable transmitter parameters, which may include values of components in matching networks or bias voltages in the power amplifier or the power amplifier driver, so as to reduce the deviation and thereby improve the impedance matching. The load current of the power amplifier may alternatively be sensed by measuring the duty cycle of its switching mode power supply. A transmitter having a power amplifier and one or more tunable circuit elements incorporates an error detector that senses the amplitude or phase of a load current and a controller that adjusts one or more tunable parameters to reduce impedance mismatch.

Abstract: An embodiment of the present invention provides transmitter having a phase locked loop that has a dynamically controllable loop bandwidth. A transmit modulator is coupled to the PLL for performing vector modulation in response to transmission symbols. Each transmission symbol comprises an amplitude signal and a phase signal. A controller is coupled to the PLL and to the transmit modulator and is operable to detect when a criteria of the transmission symbols crosses a threshold and to adjust loop bandwidth in response to crossing the threshold. The criteria of the transmission symbols may be a function of the amplitude signal or a function of the phase signal, and may be the amplitude signal, a first derivative of the amplitude signal, a second derivative of the amplitude signal, a square of the amplitude signal, a derivative of the amplitude signal squared, the phase signal, or a derivative of the phase signal.

Abstract: A circuit for detecting a serial signal comprises a first circuit coupled to receive the serial signal during a predetermined plurality of time periods of substantially equal duration. The first circuit is coupled to receive a first code. The first circuit is arranged to compare a part of the serial signal corresponding to each time period of the plurality of timer periods to the first code, thereby producing a match signal. The first circuit accumulates the match signal from each of the each time period of the plurality of time periods.

Abstract: A method of increasing linearity of an RF signal receive path includes measuring a signal amplified by the receive path. The receive path has a local oscillator operating at an LO frequency and a ground. An error signal is determined from the amplified signal, the error signal being representative of the nonlinearity. An anti-spur tone is injected into the ground. The anti-spur tone has a frequency about equal to the LO frequency and an amplitude and phase that are determined to increase the linearity of the receive path.

Abstract: System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network, computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.

Abstract: An automatic power tuning system and method, and a transmitter employing either the system or the method. In one embodiment, the system includes: (1) a power detector circuit coupled to an output of a transmitter, the transmitter having an integrator with a first, reference integrator current power control input, a second, integrator capacitor power control input and a plurality of driver fingers selectably employable by a third, driver finger power control input, the power detector configured to generate signals indicating an output voltage of the transmitter and (2) a digital processing circuit coupled to the power detector circuit and configured to employ the signals to determine at least near-optimum reference integrator current and integrator capacitor settings and select a number of driver fingers to employ to drive the output voltage.