Patents Represented by Attorney Ronald P. Rader, Fishman & Grauer Kananen
-
Patent number: 5980350Abstract: The present invention provides a cathode-ray tube provided with an electron gun capable of emitting electron beams of vertically elongate cross section.A beam control electrode (G2) is fabricated by forming beam passage holes (22R, 22G, 22B) in thin portions (20R, 20G, 20B) of a reduced thickness of an electrode plate (18), and forming excess metal relieving slots (40R to 45B) on the opposite sides of the beam passage holes (22R, 22G, 22B), respectively. An electron gun employing the beam control electrode (G2) is capable of automatically correcting the cross section of beams so that the beams form substantially circular spots in the periphery of a screen. Thus, the deterioration of picture quality attributable to the distortion of the cross section of the beams can be avoided and pictures can be displayed in an improved picture quality.Type: GrantFiled: February 2, 1999Date of Patent: November 9, 1999Assignee: Sony CorporationInventors: Yasunobu Amano, Yuichi Suzuki, Koichi Tahara
-
Patent number: 5979037Abstract: A mounting assembly and method for locating and assembling parts with a tight press fit uses an intentional design interference between two mating parts. Because of the interference fit, material is "crushed" or compressed when one mating part, such as a button frame, is forced upon the other mating part, such as a cabinet, and a tight fit is created. The interference fit is provided between first and second bosses and first and second mating holes, respectively, on opposite sides of each of the first and second bosses along a respective first axis, but not along a second axis that extends between the first and second bosses. Thus, a greater design tolerance is permitted in a direction between the first and second bosses and between the first and second mating holes, respectively. A third assembly part, such as a light guide, can be sandwiched between the first and second mating parts.Type: GrantFiled: February 6, 1997Date of Patent: November 9, 1999Assignees: Sony Corporation, Sony Electronics, Inc.Inventor: Michael Andrew Lopez
-
Patent number: 5981376Abstract: A method of forming a viahole in an interlayer insulating film without the formation of irregularities on a side wall of the viahole. The method includes a first step of forming a viahole in an interlayer insulating film having a multi-layer structure of plural kinds of insulating layers; a second step of forming a side wall film on a side wall of the viahole; and a third step of removing a native oxide film formed on a bottom portion of the viahole by etching.Type: GrantFiled: October 17, 1996Date of Patent: November 9, 1999Assignee: Sony CorporationInventors: Hiroshi Komatsu, Makoto Hashimoto, Motoaki Nakamura
-
Patent number: 5982091Abstract: A flat display apparatus provided with emitter electrodes for emitting electrons and gate electrodes for controlling the electrons emitted from the emitter electrodes, the emitter electrodes and the gate electrodes being formed on the same plane at positions facing a fluorescent screen.Type: GrantFiled: December 19, 1995Date of Patent: November 9, 1999Assignee: Sony CorporationInventor: Morikazu Konishi
-
Patent number: 5978552Abstract: An existing table may be read as table data by the position beam of a printer of a wordprocessor, a table may be read by an image input unit such as an image scanner, or may be created using a keyboard. The read or created table data is converted into code data which is stored in a memory. When the stored code data is subsequently read from the memory, the corresponding table can be displayed on an LCD unit, and the user can enter desired data in the displayed table. Thereafter, the entered data can be printed in cells of the table.Type: GrantFiled: November 25, 1992Date of Patent: November 2, 1999Assignee: Sony CorporationInventor: Masahiro Kobori
-
Patent number: 5971149Abstract: A case for accommodating a tape cassette includes a cassette-support reference arranged with a case main body on the bottom of a cassette compartment and for supporting a shell of the tape cassette to be apart from the bottom of the cassette compartment, reel supports arranged with the case main body on the bottom of the cassette compartment and for supporting the tape reels of the tape cassette having the shell supported by the cassette-support reference to be in non-contact with the shell, and a lid arranged to close the cassette compartment of the case main body.Type: GrantFiled: March 10, 1998Date of Patent: October 26, 1999Assignee: Sony CorporationInventor: Satoshi Sakurai
-
Patent number: 5972270Abstract: A temperature sensor forming method and forming die are provided which perform insert-forming of a temperature sensor with a minimum of processes and in a short time. The temperature sensor formed has a temperature sensing element 1 arranged in a predetermined position inside a resin case 2. The process does not leave traces of pins that would allow water to penetrate the interior of the case. The process comprises a first step of supporting the temperature sensing element 1 with first and second slide blocks 6c and 6g. The process comprises a second step of injecting a molten forming resin 2a into a forming die 6 and retracting the first slide block 6c by injection pressure while the temperature sensing element 1 is being supported by the second slide block 6g. The process comprises a third step of retracting the second slide block 6g while injecting the molten forming resin 2a into the forming die 6.Type: GrantFiled: June 12, 1998Date of Patent: October 26, 1999Assignee: Niles Parts Co., Ltd.Inventors: Seiichi Furuya, Takeshi Sakamaki, Hiroyuki Yamauchi
-
Patent number: 5969990Abstract: A semiconductor nonvolatile memory device where a main bit line is divided into a plurality of sub bit lines via operational connecting means, memory transistors connected to the sub bit lines are arranged in the form of a matrix, and control gate electrodes of these memory transistors are connected to word lines, provided with a means for setting sub bit lines at a programming prohibit potential at the time of a data programming operation; a means for causing a discharge in a selected sub bit line among the sub bit lines set to the programming prohibit potential and placing the non-selected sub bit lines among the sub bit lines in a floating state; and a means for supplying a program voltage to the selected word line.Type: GrantFiled: January 29, 1998Date of Patent: October 19, 1999Assignee: Sony CorporationInventor: Kenshiro Arase
-
Patent number: 5968305Abstract: Bonding of a plurality optical recording substrates in multi-layered optical recording mediums are facilitated by using ultraviolet lasers in a line-by-line manner such as telecentric scanning, raster scanning, circular scanning, or the like.Type: GrantFiled: October 24, 1997Date of Patent: October 19, 1999Assignees: Sony Corporation, Sony Electronics, Inc.Inventor: Glenn J. Maenza
-
Patent number: 5967889Abstract: A fixture for holding a semiconductor chip during a polishing process can be made to also hold the chip while the chip is inspected by a scanning electron microscope. In this manner, the polishing of the chip may be inspected and monitored without removing the chip from the polishing fixture. This allows polishing to be resumed, if necessary, with more precision. This results because the position of the chip with respect to the polishing fixture has not been altered by removing and then resecuring the chip as would be otherwise necessary for microscopic inspection of the chip.Type: GrantFiled: May 16, 1997Date of Patent: October 19, 1999Assignees: Sony Corporation, Sony Electronics, Inc.Inventor: Victor Tikhonov
-
Patent number: 5966068Abstract: A novel pager and paging system assist a traveler, particularly a business traveler, with itinerary reminders and information regarding local services that is coordinated to the place and time of the items on the traveler's schedule. The paging system includes a database of the traveler's itinerary information and a database of information regarding locally available services. Items from the itinerary database are matched with similarly located or related services and transmitted to the traveler's pager in a timely manner to remind the traveler of his or her schedule and commitments.Type: GrantFiled: March 18, 1997Date of Patent: October 12, 1999Assignees: Sony Corporation, Sony Electronics, Inc.Inventors: James E. Wicks, David Fine
-
Patent number: 5963668Abstract: Polygonal data input in a first step is subjected to evaluation in which all edges of the polygon data are ranked in importance on the basis of a volume change caused by removal of that edge. The edges are sorted on the basis of an evaluation value in a third step. In a fourth step, the edge of a small evaluation value is determined to be an edge of a small influence on the general shape and is removed. In a fifth step, a new vertex is determined from the loss of vertex by the edge removal. In a sixth step, a movement of texture coordinates and a removal of the texture after the edge removal are executed on the basis of the area change of the texture due to the edge removal by a predetermined evaluating function. In a seventh step, by repeating the processes in the second to sixth steps, a polygon model approximated to a desired layer can be obtained.Type: GrantFiled: November 25, 1996Date of Patent: October 5, 1999Assignee: Sony CorporationInventors: Junji Horikawa, Takashi Totsuka
-
Patent number: 5962084Abstract: A plasma CVD process of forming a metal film containing a residual halogen element in a small amount and a high reliability semiconductor device fabricated by the process. The plasma CVD process includes the step of forming a metal film on a substrate to be processed, using a mixed gas containing a metal halide and hydrogen, wherein the plasma CVD process adopts a plasma CVD condition which is determined in such a manner that emission spectrum intensities of a plasma of the mixed gas are measured; and a mixing ratio of the metal halide in the mixed gas is set to be not more than a value at which a decreasing rate, depending on mixing of the metal halide, of an emission spectrum intensity of a hydrogen spectral line is rapidly changed and also at which an increasing ratio, depending on mixing of the metal halide, of an emission spectrum intensity of a halogen element is rapidly changed.Type: GrantFiled: December 20, 1996Date of Patent: October 5, 1999Assignee: Sony CorporationInventors: Takaaki Miyamoto, Shingo Kadomura, Atsushi Kawashima
-
Patent number: 5958632Abstract: A method of making a mask pattern is provided for achieving an alignment mark closer to the size of design pattern with any mask material and with any type and size of target pattern so that overlay accuracy of micro target pattern is improved. Sizing processing is performed on an alignment mark pattern (design pattern) in each step of pattern formation process, depending on a mask material (resist) and a type and a size of a target pattern. A sizing pattern thereby formed is printed on a mask substrate. The form and size of printed pattern is substantially equal to the alignment mark pattern of the design size.Type: GrantFiled: June 25, 1998Date of Patent: September 28, 1999Assignee: Sony CorporationInventor: Atsushi Sekiguchi
-
Patent number: 5960312Abstract: In the process for removing an insulating film formed at the surface where the semiconductor is exposed at the bottom of the contact with the progress of heat treatment for activation annealing of impurity doped to the semiconductor surface which has been executed after a multilayer insulating film is formed on a semiconductor substrate, a contact region is etched to form a contact aperture which reaches the semiconductor substrate and impurity is doped to the semiconductor substrate surface to form a protection film at the side wall of the aperture, it can be prevented that contact aperture is deformed and ohmic contact is no longer formed easily because the side wall of contact is etched ununiformly. Moreover, it can also be prevented that the contact is enlarged in size.Type: GrantFiled: April 26, 1996Date of Patent: September 28, 1999Assignee: Sony CorporationInventor: Takafumi Morikawa
-
Patent number: 5952736Abstract: A pulse output circuit which has an output stage connected to a capacitive load capable of improving a through-rate of an input pulse signal with reduced power consumption is provided.Type: GrantFiled: September 17, 1998Date of Patent: September 14, 1999Assignee: Sony CorporationInventor: Yoshiaki Matsubara
-
Patent number: 5949326Abstract: A novel paging technology allows a pager user limited wireless access to the internet via a paging system. The pager user may file an interest profile with the pager system service provider listing internet sites from which the pager user desires information. The service provider may access those sites and provide the information to the subscriber's pager either regularly or when signalled to do so by the pager user. The pager may further include an input device, such as a virtual keyboard, with which e-mail or chat room messages may be entered. The pager then transmits the messages to the paging system which conveys them to the internet.Type: GrantFiled: February 13, 1997Date of Patent: September 7, 1999Assignees: Sony Corporation, Sony Electronics, Inc.Inventors: James E. Wicks, Eduardo Sciammarella
-
Patent number: 5949033Abstract: A loudspeaker enclosure having a constrained layer damping system for minimizing the propagation of vibrations and controlling the resonant modes of the enclosure. The enclosure has a front baffle board on which a plurality of transducers are mounted, and a plurality of other walls mounted to the baffle board to form a cabinet structure. The front baffle board comprises an interior substrate, an exterior substrate, and a constrained layer damping material sandwiched between and bonded to the two substrates. The constrained layer damping material comprises an energy absorbing thermoplastic alloy having a very high material loss factor. The other walls of the enclosure also comprise an interior substrate and an exterior substrate with a constrained layer damping material sandwiched therebetween. An extensional damping material may also be bonded to an interior surface of the interior substrates to further control vibrations in the enclosure.Type: GrantFiled: October 30, 1996Date of Patent: September 7, 1999Assignees: Sony Corporation, Sony Electronics, Inc.Inventor: Daniel P. Anagnos
-
Patent number: 5945856Abstract: A clock control circuit 10 generates a reference clock signal CK.sub.2 in accordance with a clock signal CLK, performs a phase comparison with an oscillation signal S50 from a programmable mask generation circuit 50 at a phase comparator 20, generates an up signal S.sub.up or a down signal S.sub.dw in accordance with the result of comparison, and outputs the same to a counter 30. The counter 30 sequentially determines values of the bits from the most significant bit to the least significant bit, outputs the count S30 to a digital control delay line 40, and controls the frequency of an oscillation signal S40. After reaching the locked state, the counter 30 sequentially determines the values of bits from the least significant bit to the most significant bit in accordance with the up/down signal and tracks the reference clock signal CK.sub.2, therefore the lock up time of the digital PLL circuit can be shortened.Type: GrantFiled: June 24, 1997Date of Patent: August 31, 1999Assignee: Sony CorporationInventor: Hiroshi Yanagiuchi
-
Patent number: 5943592Abstract: A making method of a semiconductor device comprising the step of forming a first silicon layer on a silicon substrate, forming a second silicon layer comprising amorphous silicon on the first silicon layer, then crystallizing the second silicon layer and further forming a conductive layer made of a metal silicide or a metal on the second silicon layer, wherein the method comprises forming an intermediate layer to the surface of the first silicon layer after forming the first silicon layer and before forming the second silicon layer, in which the interlayer film has a film thickness within such a range as electrons are conducted by direct tunneling and such a film thickness as disconnecting the succession of the crystallinity of the first silicon layer upon crystallization of the second silicon layer. Accordingly, fluctuation of Vth caused by inter-diffusion of impurities by way of the metal silicide layer is reduced in CMOS of the dual layered polysilicon polycide structure is decreased.Type: GrantFiled: June 10, 1997Date of Patent: August 24, 1999Assignee: Sony CorporationInventors: Masanori Tsukamoto, Kazuhiro Tajima