Patents Represented by Attorney Rosemary L. S. Pike
  • Patent number: 6841441
    Abstract: A method of fabricating first and second gates comprising the following steps. A substrate having a gate dielectric layer formed thereover is provided. The substrate having a first gate region and a second gate region. A thin first gate layer is formed over the gate dielectric layer. The thin first gate layer within the second gate region is masked to expose a portion of the thin first gate layer within the first gate region. The exposed portion of the thin first gate layer is converted to a thin third gate layer portion. A second gate layer is formed over the thin first and third gate layer portions. The second gate layer and the first and third gate layer portions are patterned to form a first gate within first gate region and a second gate within second gate region.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: January 11, 2005
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Chew Hoe Ang, Eng-Hua Lim, Randall Cher Liang Cha, Jia Zhen Zheng, Elgin Quek, Mei-Sheng Zhou, Daniel Yen
  • Patent number: 6835989
    Abstract: Methods for forming dual-metal gate CMOS transistors are described. An NMOS and a PMOS active area of a semiconductor substrate are separated by isolation regions. A metal layer is deposited over a gate dielectric layer in each active area. Oxygen ions are implanted into the metal layer in one active area to form an implanted metal layer which is oxidized to form a metal oxide layer. Thereafter, the metal layer and the metal oxide layer are patterned to form a metal gate in one active area and a metal oxide gate in the other active area wherein the active area having the gate with the higher work function is the PMOS active area. Alternatively, both gates may be metal oxide gates wherein the oxide concentrations of the two gates differ. Alternatively, a dummy gate may be formed in each of the active areas and covered with a dielectric layer. The dielectric layer is planarized thereby exposing the dummy gates. The dummy gates are removed leaving gate openings to the semiconductor substrate.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: December 28, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Wenhe Lin, Mei-Sheng Zhou, Kin Leong Pey, Simon Chooi
  • Patent number: 6835609
    Abstract: A method of forming a double gated SOI channel transistor comprising the following steps. A substrate having an SOI structure formed thereover is provided. The SOI structure including a lower SOI silicon oxide layer and an upper SOI silicon layer. The SOI silicon layer is patterned to form a patterned silicon layer. A dummy layer is formed over the SOI silicon oxide layer and the patterned SOI silicon layer. The dummy layer is patterned to form a damascene opening therein exposing: a portion of the lower SOI silicon oxide layer; and a central portion of the patterned SOI silicon layer to define a source structure and a drain structure. Patterning the exposed lower SOI silicon oxide layer to form a recess. Gate oxide layer portions are formed around the exposed portion of the patterned SOI silicon layer. A planarized layer portion is formed within the final damascene opening. The planarized layer portion including a bottom gate and a top gate.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: December 28, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yong Meng Lee, Da Jin, Mau Lam Lai, David Vigar, Siow Lee Chwa
  • Patent number: 6835631
    Abstract: A method of enhancing inductor performance comprising the following steps. A structure having a first oxide layer formed thereover is provided. A lower low-k dielectric layer is formed over the first oxide layer. A second oxide layer is formed over the lower low-k dielectric layer. The second oxide layer is patterned to form at least one hole there through exposing a portion of the lower low-k dielectric layer. Etching through the exposed portion of the lower low-k dielectric layer and into the lower low-k dielectric layer to from at least one respective air gap within the etched lower low-k dielectric layer. An upper low-k dielectric layer is formed over the patterned second oxide layer. At least one inductor is formed within the upper low-k dielectric layer and over the at least one air gap whereby the performance of the inductor is enhanced.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: December 28, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd
    Inventors: Zheng Jia Zhen, Sanford Chu, Ng Chit Hwei, Lap Chan, Purakh Raj Verma
  • Patent number: 6830971
    Abstract: A process of fabricating high dielectric constant MIM capacitors. The high dielectric constant MIM capacitors are for both RF and analog circuit applications. For the high dielectric constant MIM capacitors, the metal is comprised of copper electrodes in a dual damascene process. The dielectric constant versus the total thickness of super lattices is controlled by the number of artificial layers. Dielectric constants near 900 can be achieved for 250 Angstrom thick super lattices. MBE, molecular beam epitaxy or ALCVD, atomic layer CVD techniques are employed for the layer growth processes.
    Type: Grant
    Filed: November 2, 2002
    Date of Patent: December 14, 2004
    Assignee: Chartered Semiconductor Manufacturing LTD
    Inventors: Subramanian Balakumar, Chew Hoe Ang, Jia Zhen Zheng, Paul Proctor
  • Patent number: 6830966
    Abstract: A device and method are described for forming a grounded gate NMOS (GGNMOS) device used to provide protection against electrostatic discharge (ESD) in an integrated circuit (IC). The device is achieved by adding n-wells below the source and drain regions. By tailoring the dopant concentration profiles of the p-well and n-wells provided in the fabrication process, peak dopant concentrations are moved below the silicon surface. This moves ESD conduction deeper into the IC where thermal conductivity is improved, thereby avoiding thermal damage occurring with surface conduction. The device does not require a salicidation block or additional implantation and uses standard NMOS fabrication processing steps, making it advantageous over prior art solutions.
    Type: Grant
    Filed: June 12, 2002
    Date of Patent: December 14, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Jun Cai, Keng Foo Lo
  • Patent number: 6828082
    Abstract: A method of forming small features, comprising the following steps. A substrate having a dielectric layer formed thereover is provided. A spacing layer is formed over the dielectric layer. The spacing layer has a thickness equal to the thickness of the small feature to be formed. A patterned, re-flowable masking layer is formed over the spacing layer. The masking layer having a first opening with a width “L”. The patterned, re-flowable masking layer is re-flowed to form a patterned, re-flowed masking layer having a re-flowed first opening with a lower width “1”. The re-flowed first opening lower width “1” being less than the pre-reflowed first opening width “L”. The spacing layer is etched down to the dielectric layer using the patterned, re-flowed masking layer as a mask to form a second opening within the etched spacing layer having a width equal to the re-flowed first opening lower width “1”. Removing the patterned, re-flowed masking layer.
    Type: Grant
    Filed: February 8, 2002
    Date of Patent: December 7, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Chew-Hoe Ang, Eng Hua Lim, Randall Cha, Jia-Zhen Zheng, Elgin Quek, Mei-Sheng Zhou, Daniel Yen
  • Patent number: 6828635
    Abstract: An improved NPN bipolar transistor integratable with CMOS FET processing is achieved. The transistor is formed on a substrate using a CMOS process and one additional masking and implant step. The CMOS N wells are used to form the collector contacts (reachthrough) and the P wells are used to form the base. N doped third wells are formed under the N wells, P wells, and shallow trench isolation regions to provide subcollectors. Since the P wells are not implanted through the STI, basewidths are reduced and current gain is increased. Gate electrode masking elements, formed over the base, separate the emitter and base contact regions, improving the emitter-to-base breakdown voltage. The CMOS source/drain N type implants then form emitters in the emitter regions and ohmic contacts in the collector contacts. The source/drain P type implants form the ohmic base contacts to complete the bipolar transistor.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: December 7, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Shesh Mani Panday, Alan Shafi, Yong Ju
  • Patent number: 6828194
    Abstract: A new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A tunneling oxide layer is formed overlying a semiconductor substrate. A first polysilicon layer, an interpoly oxide layer and then a second polysilicon layer are deposited. A second polysilicon layer is deposited overlying the interpoly oxide layer. The second polysilicon layer, the interpoly oxide layer, the first polysilicon layer, and the tunneling oxide layer are patterned to form control gates and floating gates for planned Flash EEPROM memory cells. Ions are implanted to form drain junctions where the drain junctions are shallow and abrupt. Ions are implanted to form angled pocket junctions adjacent to the drain junctions. The angled pocket junctions are implanted at a non-perpendicular angle with respect to the semiconductor substrate and are counter-doped to the drain junctions. Ions are implanted to form source junctions that are deeper and less abrupt than the drain junctions.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: December 7, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Tze Ho Simon Chan, Yung-Tao Lin
  • Patent number: 6821904
    Abstract: In accordance with the objectives of the invention a new method is provided for the creation of layers of gate oxide having an unequal thickness. Active surface regions are defined over the surface of a substrate, a thick layer of gate oxide is grown over the active surface. A selective etch is applied to the thick layer of gate oxide, selectively reducing the thickness of the thick layer of gate oxide to the required thickness of a thin layer of gate oxide. The layer of thick gate oxide is blocked from exposure. N2 atoms are implanted into the exposed surface of the thin layer of oxide, rapid thermal processing is performed and the blocking mask is removed from the surface of the thick layer of gate oxide. A high concentration of nitride has now been provided in the thin layer of gate oxide.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: November 23, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yelehanka Ramachandramurthy Pradeep, Sanford Chu, Chit Hwei Ng, Jia Zhen Zheng, Purakh Verma
  • Patent number: 6822268
    Abstract: A method of fabricating an LCD-on-silicon pixel device, comprising the following steps. A substrate having an upper layer of silicon is provided. A via is formed in the silicon layer. An opaque conducting layer is deposited over the silicon layer, filling the via. The opaque conducting layer is planarized a reflective layer is deposited over the opaque conducting layer. Alternatively, the via may be formed by a deposition and etch back process with one metal. An opaque conducting layer is then deposited and planarized before deposition of the reflective layer. An LCD-on-silicon pixel device, comprises a substrate having an upper silicon layer. The upper silicon layer has a plug therein comprised of an opaque conducting material. Over the upper silicon layer and the opaque conducting plug is a planar opaque conducting layer and a planar reflective layer is over the planar opaque conducting layer.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: November 23, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yung-Tao Lin, Sik On Kong
  • Patent number: 6821888
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: November 23, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yakub Aliyu, Simon Chooi, Meisheng Zhou, John Sudijono, Subhash Gupta, Sudipto Ranendra Roy
  • Patent number: 6821886
    Abstract: A new method is provided for the creation of an adhesion/barrier layer over which a tungsten interconnect is created. The invention reduces metal extrusion and effects of pin-holes by dividing the process of barrier material of TiN deposition into phases, whereby after about half the thickness of the required layer of TiN has been deposited, an intermediate and very thin layer of Ti is deposited. After the thin layer of Ti has been deposited, the deposition of the barrier layer of TiN is continued to the point where the required thickness for the layer of TiN has been reached.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: November 23, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Nace Layadi, Alvaro Maury, Jovin Lim
  • Patent number: 6814812
    Abstract: A double acting cold trap equipped with a set of exhaust gas condensing fins and a set of exhaust gas condensing plates is disclosed. The invention also discloses a double acting cold trap that incorporates a deflecting plate to direct the exhaust gases over the condensing fins and plates in a serial fashion. This increases the efficiency of the collection of unwanted particles.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: November 9, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Wei Hua Tong, Chen Yu Yang, Zhang Jian, Qian Wu Quan
  • Patent number: 6815239
    Abstract: Five new methods for the formation of an improved liquid-crystal-on-silicon display are described, in which the device structure is enhanced by the photolithographic building of alignment posts among the mirror pixels of the micro-display. These five methods accommodate the fabrication of an optical interference multilayer, which improves the image quality of the reflected light. These five methods are: Silicon Dioxide Posts by Wet Etching. Amorphous Silicon Posts by Plasma Etching. Silicon Nitride Posts by Plug Filling. Insulation Material Posts by Lift-off. Polyimide Posts by Photosensitive Etching.
    Type: Grant
    Filed: March 5, 1999
    Date of Patent: November 9, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Sik On Kong, Rajan Rajgopal, George Wong
  • Patent number: 6815823
    Abstract: A new method and structure is provided for the creation of interconnect lines. The cross section of the interconnect lines of the invention, taken in a plane that is perpendicular to the longitudinal direction of the interconnect lines, is a triangle as opposed to the conventional square or rectangular cross section of interconnect lines.
    Type: Grant
    Filed: October 6, 2003
    Date of Patent: November 9, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Young-Way Teh, Victor Seng Keong Lim, Ting Cheong Ang
  • Patent number: 6815355
    Abstract: A process for fabricating a complimentary metal oxide semiconductor (CMOS), device featuring composite insulator spacer shapes which allow P channel (PMOS), short channel effects to be minimized, and allow reductions in resistance for N channel (NMOS), source/drain extension regions to be realized, has been developed. The process features initial composite insulator spacers formed in the sides of gate structures after definition of the NMOS and PMOS source/drain extension regions. The initial composite insulator spacer, comprised of an underlying silicon oxide component, an L-shaped silicon nitride component, and an overlying doped oxide component, is then used for definition of the PMOS heavily doped source/drain region, allowing for adequate space between the heavily doped source/drain and channel regions, thus reducing the risk of short channel effects.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: November 9, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventor: Elgin Quek
  • Patent number: 6809935
    Abstract: A new method is provided for mounting a semiconductor on the surface of a Printed Circuit Board. A layer of Elastomer is deposifed on the surface face of the PCB, this layer of Elastomer makes the PCB into a thermally compliant PCB such that the thermal mismatch between the PCB and the semiconductor die that is mounted on the PCB is sharply reduced. Openings are created in the layer of Elastomer and electrical interfaces are created such that the PCB can be connected to the semiconductor die that is mounted on the PCB.
    Type: Grant
    Filed: October 10, 2000
    Date of Patent: October 26, 2004
    Assignee: Megic Corporation
    Inventor: Jin-Yuan Lee
  • Patent number: 6806570
    Abstract: A thermally compliant multi-layer wiring structure on a semiconductor chip is described. The multi-layer wiring structure incorporates an “empty” or air gap under the interconnect wiring and does not allow any thermally induced strains to be transmitted to the interconnecting solder balls. This design is to be used in chip scale packaging applications where printed circuit technology is used as the next level of package.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: October 19, 2004
    Assignee: Megic Corporation
    Inventors: Jin-Yuan Lee, Eric Lin
  • Patent number: 6804149
    Abstract: The present invention relates to a nonvolatile memory cell and/or array and a method of operating the same high integrated density nonvolatile memory cell enabling high integration density, low voltage programming and/or high speed programming, a method of programming same and a nonvolatile memory array. A p-well 101 is formed in a surface of a substrate 10 and a channel forming semiconductor region 110 is defined in a surface of the p-well 101 and separated by a first n+ region 121 and a second n+ region 122. A carrier-supplying portion (CS: carrier supply) 111 is formed coming into contact with the first n+ region 121 and a carrier-acceleration-injection portion 112 (AI: acceleration and injection) is in contact with the second n+ region 122 in the channel forming semiconductor region 110 wherein the carrier-supplying portion 111 and carrier-acceleration-injection portion 112 are in contact with each other.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: October 12, 2004
    Assignee: New Halo, Inc.
    Inventors: Seiki O. Ogura, Yutaka Hayashi