Patents Represented by Attorney, Agent or Law Firm Rosenthal & Osha L.L.P.
  • Patent number: 6801049
    Abstract: A fault analysis method and apparatus which is able to improve the reliability of fault analysis of semiconductor integrated circuit. In case of supplying a test pattern sequence having a plurality of test patterns to the semiconductor IC, an analysis point whose electric potential changes according to the change of supplied test pattern is placed corresponding to the test pattern sequence. Then, a transient power supply current generated on the semiconductor IC according to the change of the test pattern is measured and determined whether the measured transient power supply current is abnormal or not. A defection point is presumed based on the test pattern sequence where the transient power supply current is abnormal, and the analysis point placed corresponding to the test pattern sequence.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: October 5, 2004
    Assignee: Advantest Corporation
    Inventors: Masahiro Ishida, Takahiro Yamaguchi, Yoshihiro Hashimoto
  • Patent number: 6791389
    Abstract: According to the present invention, a variable delay circuit includes a delay circuit unit group, a control unit and an offset delay amount memory group. The delay circuit unit group includes a plurality of delay circuit units, and the plurality of delay circuit units includes two paths having different delay amounts. The offset delay amount memory group includes a plurality of offset delay amount memories, and offset delay amounts corresponding to delay amounts of the first paths of the corresponding delay circuit units are set in the plurality of offset delay amount memories. The control unit includes a plurality of subtracting units, and the plurality of subtracting units select paths of the delay circuit units through which an input signal may pass by using a delay setting value and offset delay amounts. It is possible to reduce volume of the circuit and remove a table since the path is selected by calculation.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: September 14, 2004
    Assignee: Advantest Corporation
    Inventors: Hiroyuki Mikami, Yasutaka Tsuruki
  • Patent number: 6778027
    Abstract: A phase locked loop that includes a receiver circuit for matching delays of a system clock and a feedback clock at an input of the phase locked loop is provided. The receiver circuit employs system clock path circuitry to input the system clock and feedback clock path circuitry to input the feedback clock, where current flow and load resistances associated with the system clock path circuitry and current flow and load resistances associated with the feedback clock path circuitry control the generation of substantially delay matched system and feedback clocks.
    Type: Grant
    Filed: April 12, 2002
    Date of Patent: August 17, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Claude Gauthier, Pradeep Trivedi, Brian Amick
  • Patent number: 6779131
    Abstract: The present invention relates to a method and apparatus for a reconfigurable multi-chip module. The reconfigurable multi-chip module includes a processor; a memory module connected to the processor; and a memory control component for controlling whether the processor uses the memory module. The method of producing multi-chip modules includes assembling a processor and a memory module on the multi-chip module; testing the memory module; and selectively configuring the processor to use the memory module based on the testing of the memory module.
    Type: Grant
    Filed: May 1, 2001
    Date of Patent: August 17, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Rambabu Pyapali, Xuejun Yuan, Xiaowei Jin, Peter Lai, Samer H. Haddad, Jeffrey Wong
  • Patent number: 6769083
    Abstract: A test pattern generator for generating a test pattern for testing electrical characteristics of an electrical device. The test pattern generator comprises a pattern memory (32), a pattern cache memory (54, 180 and 182), a vector memory (12), a read out controller (14 and 170), and a transfer controller (34 and 178). The pattern memory (32) stores the test pattern. The pattern cache memory (54, 180 and 182) stores the test pattern read out from the pattern memory (32). The vector memory (12) stores a vector instruction indicating an order of the test pattern to be generated. The read out controller (14 and 170) judges whether an address of the test pattern to be read out from the pattern memory (32) is to be jumped or not based on the vector instruction read out from the vector memory (12).
    Type: Grant
    Filed: November 10, 1999
    Date of Patent: July 27, 2004
    Assignee: Advantest Corporation
    Inventors: Masaru Tsuto, Tatsuya Yamada
  • Patent number: 6762504
    Abstract: The present invention provides an adhesive film for producing an electric device having high reliability. Release agent layer of release film of the present invention is based on a fluorine compound with no silicone oil so that the adhesive force between substrate and release agent layer is enough high to provide an electric device having high reliability wherein release agent layer is not adhered when release film is separated from adhesive layer. The surface roughness of substrate of 3 &mgr;m or less limits irregularities on the side of adhesive layer from which release film has been separated and therefore, no bubbles occur between adhesive layer and semiconductor chip when semiconductor chip is pressed against adhesive layer. If the surface roughness of substrate is 1 &mgr;m or more, adhesive film also has high slitting performance.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: July 13, 2004
    Assignee: Sony Chemicals Corp.
    Inventor: Yukio Yamada
  • Patent number: 6756599
    Abstract: A particle-optical apparatus for changing trajectories of charged particles of a divergent particle beam oriented along a longitudinal axis is proposed, comprising: an inner electrode arrangement which is at least partially transparent for the particles, engages at least partially around the longitudinal axis with a radial distance and extends along the longitudinal axis, an outer electrode arrangement which engages at least partially around the inner electrode arrangement with a radial distance and extends along the longitudinal axis, and a voltage source for providing a potential difference between the inner and the outer electrode arrangements, wherein the voltage source provides such a potential difference that a kinetic component of a particle traversing the inner electrode arrangement is reversible, said kinetic component being oriented orthogonally to the longitudinal axis.
    Type: Grant
    Filed: April 4, 2002
    Date of Patent: June 29, 2004
    Assignee: Carl Zeiss SMT AG
    Inventor: Oliver Kienzle
  • Patent number: 6753740
    Abstract: A calibration and adjustment system for post-fabrication control of a phase locked loop bias-generator is provided. The calibration and adjustment system includes an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired phase locked loop performance characteristic after the phase locked loop has been fabricated. A representative value of the amount of adjustment desired in the bias-generator output may be stored and subsequently read to adjust the phase locked loop.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: June 22, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Claude Gauthier, Brian W. Amick, Pradeep Trivedi, Dean Liu
  • Patent number: 6747485
    Abstract: A sense amplifier type input receiver includes a differential receiver circuit operatively coupled to an output stage. The output stage includes a pass gate enabled latch. The differential receiver circuit may output a first differential output and a second differential output. The output stage may include a first pass gate operatively coupled between the first differential output and an output of the output stage, a second pass gate operatively coupled between the second differential output and the pass gate enabled latch, and the pass gate enabled latch may be operatively coupled to the output of the output stage.
    Type: Grant
    Filed: June 28, 2000
    Date of Patent: June 8, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Samudyatha Suryanarayana, Gajendra P. Singh
  • Patent number: 6738047
    Abstract: To save trouble in replacing cards and to facilitate the operation of a key on a home page, a home page display system according to the invention includes terminal equipment connected to the Internet, a remote control that transmits data to the terminal equipment, an IC card installed in the remote control and a TV monitor on which a home page corresponding to the IC card is displayed. The remote control is provided with a transparent tablet and when the IC card is set, a key control panel printed on the surface of the card appears in the part of the tablet. A program for allocating each key on the tablet corresponding to a home page is stored in the IC card.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: May 18, 2004
    Assignee: Funai Electric Co., Ltd.
    Inventor: Hideo Kobayashi
  • Patent number: 6734513
    Abstract: In one embodiment, a semiconductor device having single or multi-layer intermediate layers that easily adhere to a glass frit and lead lines of respective interconnections is disclosed. In general, the single or multi-layer intermediate layers are formed on at least the top surfaces of portions of the respective lead lines on which the glass frit is placed.
    Type: Grant
    Filed: November 1, 2001
    Date of Patent: May 11, 2004
    Assignee: Omron Corporation
    Inventors: Tomonori Seki, Tomonari Kogure
  • Patent number: 6733320
    Abstract: A contact 4 for a PGA socket 1 is formed with a plate-like base portion 41, a pair of projecting portions 42a, 42b provided continuously at one end of the base portion 41 to extend in a direction substantially equal to the base portion, a turned portion 43 provided continuously at the other end of the base portion 41 to face the base portion 41, and a tail portion 44 provided continuously at the other end of the base portion 41 not to face the base portion 41. The turned portion 43 is provided with a contact portion 43a contacting a pin of a PGA package on a surface of the turned portion 43 not facing the base portion 41. This prevents flux from adhering on the contact portion 43a of the contact 4 when the contact 4 is soldered on a board.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: May 11, 2004
    Assignee: J.S.T. Mfg. Co., Ltd.
    Inventors: Hiroaki Kukita, Yoshifumi Nishida
  • Patent number: 6729418
    Abstract: A back reaming tool is disclosed which includes a tool body adapted to be coupled to a drill string, and at least one roller cone rotatably mounted to a leg and having cutting elements disposed thereon. The leg is removably coupled to the tool body. The at least one roller cone is open at only one axial end thereof.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: May 4, 2004
    Assignee: Smith International, Inc.
    Inventors: Robert Harlan Slaughter, Jr., Peter Thomas Cariveau, Vincent Wayne Shotton
  • Patent number: 6727737
    Abstract: A delay locked loop design uses a diode operatively connected to a loop filter capacitor to control a leakage current of the loop filter capacitor. By positioning a diode in series with the loop filter capacitor, a voltage potential across the loop filter capacitor is reduced, thereby reducing the leakage current of the loop filter capacitor. Moreover, the leakage current of the loop filter capacitor is controlled in that it cannot exceed the current through the diode. Control and reduction of the loop filter capacitor leakage current leads to more reliable and stable delay locked loop behavior.
    Type: Grant
    Filed: July 19, 2002
    Date of Patent: April 27, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Pradeep Trivedi, Claude Gauthier, Dean Liu
  • Patent number: 6728903
    Abstract: A memory test system of the present invention comprises a plurality of memory test units 90A, 90B, . . . , which test memory devices 52 to 56, a host computer (EWS) 10 which evaluates test results of the memory devices 52 to 56, and a common memory unit 12 which connects a plurality of the memory test units 90A, 90B, . . . , to the host computer (EWS) 10. The common memory unit has an interrupt controller (INT CNT) 22. In each of the memory test units 90, a slave processor (MCPU) 40 and a memory for the slave processor (MEM) 14 are provided. MCPU 40 reads memory test results and responses of local processors (RCPU) 42 to 46 which are stored in RMEMs 32 and transfers read data to SMEM 16. MCPU 40 generates an interrupt signal. When all MCPUs 40 generate interrupt signals, INT CNT 22 generates an interrupt signal INT to the EWS 10. The EWS 10 may perform several functions based on the interrupt signal INT.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: April 27, 2004
    Assignee: Advantest Corporation
    Inventor: Yoshiaki Kato
  • Patent number: 6724164
    Abstract: A power-window control device is provided which is capable of inexpensively avoiding the occurrence of a failure, not to overlook in safety, due to a short-circuit (including current leak) at between adjacent ones of switch terminals. The switch terminals are arranged in a combination that the terminals having a possibility to cause a failure due to short-circuit are not in an adjacent relationship. Specifically, in the case of a configuration of FIG. 1, arrangement is made such that there is no adjacent relationship between the MU and the COMA, the MD and the COMA, the NC and the COMA, the NC and the NO, the NC and the COMS, the NO and the COMA, the NO and the COMS, and the COMA and the COMS, e.g. in an order of the COMS, MD, NO, AD, COMA, AU, NC and MU.
    Type: Grant
    Filed: June 18, 2003
    Date of Patent: April 20, 2004
    Assignee: Omron Corporation
    Inventors: Keiichi Shimizu, Yasuhide Tanaka
  • Patent number: 6725347
    Abstract: A memory control unit has been developed. The control unit includes a command “spin wheel” which schedules the order of read and write commands to the memory. It also includes a read “spin wheel” which ensures proper timing of the read commands and a write “spin wheel” which ensures proper timing of the write commands.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: April 20, 2004
    Assignee: Sun Microsystems, Inc.
    Inventors: Liuxi Yang, Duong Tong
  • Patent number: D489059
    Type: Grant
    Filed: June 17, 2002
    Date of Patent: April 27, 2004
    Assignee: Allied Telesis K.K.
    Inventors: Minoru Dendou, Kouki Sakata
  • Patent number: D490392
    Type: Grant
    Filed: May 28, 2003
    Date of Patent: May 25, 2004
    Assignee: Matsushita Electric Works, Ltd.
    Inventor: Takayuki Watanabe
  • Patent number: D492254
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: June 29, 2004
    Assignee: Matsushita Electric Works, Ltd.
    Inventors: Yoshiyuki Nakashima, Katsumi Kikuchi