Abstract: A disk reading apparatus includes a binarizing unit 5 for binarizing a tracking error signal 21 with a hysteresis width and for generating a track count signal 22, a jump unit 8 for causing track-jump on the basis of the track count signal 22, a malfunction detecting unit 9 for transmitting a malfunction signal 24 when level inversion occurs to the track count signal 22 while follow of the track is being implemented, and a control unit 15 for widening the hysteresis width when the pickup 1 is caused to follow the track, and for narrowing the hysteresis width when the pickup 1 is caused to track-jump.

Abstract: An integrated information appliance includes a central processing unit for executing an action in response to a user request, a storage for storing information for use by the central processing unit in responding to the user request, and a cradle which includes a scanning device for scanning an image and storing the scanned image in the storage. An information pad is removably mounted on the cradle. The information pad includes a screen display for displaying information to a user and for receiving information and requests from the user and a plurality of application buttons for sending a request to the central processing unit to perform a specific action.

Abstract: A rotary cutter mount for an earth-boring cutter includes a bearing journal adapted to be coupled to a cutter body. A first mounting end of the bearing journal is shaped to enable rotationally fixed positioning in a corresponding yoke. The yoke is operatively coupled to the body of the cutter. A ball race is formed in an exterior surface of the journal. A ball loading passage is formed in the journal. The ball loading passage has an exit hole on the race. The hole is positioned so that it is disposed in a rotary orientation which is at a selected angular displacement from the maximum radial loading on the journal. The first mounting end and the corresponding yoke are adapted to enable a plurality of rotary orientations. Each of the rotary orientations is such that the hole is oriented other than in the direction of maximum radial loading.

Abstract: A constant flow apparatus for adapting a fluid flow passing through a pipe at constant value comprises a tubular body to be mounted inside the pipe, an orifice disposed at the output end side of the tubular body, a movable needle with a flat tip portion positioned opposite the orifice, a spring supporting the needle with appropriate elastic force, and an elastic tubular sealing member having a circumferential bulging portion provided on the outside of the tubular body to cover the tubular body. The constant flow apparatus can be fixedly mounted in the pipe irrespective of the diameter of the pipe, and adapt the fluid flow passing through the pipe, preventing the needle from vibration.

Abstract: A register file design having an asymmetric bit line driver is provided. More specifically, the register file design uses a memory element that has a footer device that facilitates the discharge/charging of a bit line through a pass device, where a width of the footer device is greater than a width of the pass device. Further, a method for performing low power memory operations using asymmetric bit line drivers is provided.

Abstract: A clock detect indicator capable of determining the presence of high and low frequency clock signals is provided. The clock detect indicator, which operates independent of a reference clock, has detection circuitry that determines whether a particular clock signal has alternating high-to-low and low-to-high transitions. Based on the determination, the clock detect indicator outputs a transition on a clock detect indication signal. Further, a method for detecting a clock signal in an integrated circuit is provided.

Abstract: A protection device arranged on an electric current path between a load unit including a stabilized power supply unit and a DC power supply, includes: a switching unit including an FET having a source terminal and a drain terminal arranged on an electric current path between the DC power supply and the load unit; and an input end to which a voltage generated by the stabilized power supply circuit in the load unit as a control voltage, the control voltage being capable of turning on the FET in a case of forward connection in which a positive input terminal of the load unit is connected to an anode of the DC power supply and a negative input terminal of the load unit is connected to a cathode of the DC power supply, and turning off the FET in a case of reversed connection in which the positive input terminal of the load unit is connected to the cathode of the DC power supply and the negative input terminal of the load unit is connected to the anode of the DC power supply, wherein the control voltage is applied

Abstract: A technique that uses active shields to reduce clock skew is provided. The technique uses a shield wire for shielding the signal wire, a driver stage for driving a leading clock signal on the shielding wire, and a signal wire buffer for driving a lagging clock signal on the signal wire, where the leading clock signal is driven onto the first shield wire a phase difference before the lagging clock signal is driven onto the signal wire.

Abstract: A method for optimizing a decoupling capacitance for an on-chip temperature sensor is provided. A representative power supply waveform having noise is input into a simulation of the on-chip temperature sensor; a difference between a temperature representative input and a temperature dependent output of the on-chip temperature sensor is determined; and an amount of the decoupling capacitance is adjusted until the difference falls below a pre-selected value. A computer system for optimizing a decoupling capacitance for an on-chip temperature sensor is also provided. A computer-readable medium having recorded thereon instructions executable by a processor for optimizing a decoupling capacitance for an on-chip temperature sensor is further provided.

Abstract: A circuit reduction method that generates a netlist that maintains a topology of an original circuit while preserving an original circuit's functions and characteristics is provided. Further, a circuit reduction method that allows a user to selectively determine which nodes of an original circuit to reduce is provided. Further, a circuit reduction tool that is capable of removing loops that are not present in an original circuit but are present in an extraction of the original circuit is provided.

Abstract: Network and host efficiencies are improved by reducing the overhead associated with establishing virtual circuits. In one approach, a request for information from a client is sent to a server using a connectionless protocol such as UDP. If the requested information satisfies a policy for return by the connectionless protocol, the response is sent that way. If the policy is not satisfied, the server may reply with a message to try a connection oriented protocol such as TCP. If no response is received at all after a certain number of tries, the client will try a connection using a connection oriented protocol. In a second approach, when a request from a client is sent using a connectionless protocol, the state information for a transaction TCP (T/TCP) connection is set up in the client, giving the server the option of responding either using the connectionless protocol or using T/TCP.

Abstract: Using a distillation separator, a gas to be treated is separated into a plurality of gas groups having different boiling points. Then, the specific gases included in each of the plurality of gas groups separated at the first separator and having similar boiling points are separated using a chromatographic separator. In this manner, specific gases can be separated from the gas to be treated containing a plurality of specific gases.

Abstract: A power dissipation control mechanism for a central processing unit includes a power estimation circuit for estimating the power dissipation of instructions executed by the central processing during a selected time interval and a speed controller for adjusting the speed of the central processing unit in response to the estimated power dissipation produced by the power estimation circuit.

Abstract: An electrical connector assembly of the present invention includes a first component for supporting a first electrical connector element; a second component for supporting a second electrical connector element inserted in the first electrical connector element to be fitted therein; a short-circuit element, fitted in the first component, for electrically short-circuit the first electrical connector element; and a locking element engageable with the second component in a locked manner. The locking element is so structured that when the second component is inserted in the first component to be fitted therein, the locking element can make the short-circuit element move back to its non-short-circuit position and also can move to engage with the first component. The engagement of the locking element with the first component allows the first component and the second component to be locked against disconnection.

Abstract: A method of forming a drill bit structure, the method including fixing spacers to the drill bit structure. The spacers are arranged at preselected locations on an outer surface of the drill bit structure. A hardfacing material is then applied to the drill bit structure, and the spacers are removed. Holes are machined in the drill bit structure at the preselected locations, and drilling inserts are positioned in each hole. A method of forming a drill bit structure, the method including applying a hardfacing material to selected surfaces of the drill bit structure. The hardfacing material includes a perforated carbide infiltrated material and a perforated powder infiltrated material. The perforations in the powder infiltrated material correspond to the perforations in the carbide infiltrated material. Holes are machined in the drill bit structure at the locations of the perforations, and drilling inserts are positioned in each hole.

Abstract: A adjustment and calibration system for reducing an impedance of a power supply path of an integrated circuit is provided. The power supply path includes a first power supply line and a second power supply line to provide power to the integrated circuit. At least a digital potentiometer connected between the first power supply line and the second power supply line is adjusted to reduce the impedance of the power supply path. Control information, representative of a desired value for the digital potentiometer, is stored in a storage device. The control information stored in the storage device is subsequently selectively read out in order to adjust the digital potentiometer to a state corresponding to the control information.

Abstract: A drill bit is disclosed which includes a bit body having a plurality of ports therein arranged to provide a flow path between an interior of a drill string and the exterior of the bit body. At least one flow relief is disposed in one of the ports. The at least one flow relief is adapted to provide an increase in total flow area of the bit upon application to the bit of a selected fluid flow condition. A method for changing a total flow area of a drill bit is also disclosed, which includes pumping drilling fluid through the drill bit and operating a flow relief disposed in the bit to change the total flow area of the bit.

Abstract: A temporal delay circuit for synchronizing a source synchronous input with a local clock is provided. The source synchronous input comprises a data input and a source synchronous clock. The temporal delay circuit includes a temporal delay queue, a write pointer arranged to write the data input to the temporal delay queue based on the source synchronous clock, and a read pointer synchronized with the local clock and arranged to read from the temporal delay queue according to a desired delay.

Abstract: An interleaving AD conversion type waveform digitizer apparatus includes, in a case where the number of interleaving ways is N that is equal to or larger than two, N AD converters connected to a structure for interleaving. The sampling timings of the respective AD converters are predetermined timings corresponding to the interleaving structure so as to allow successive outputs. The digitizer receives a signal to be measured output from a device under test and performs quantization. The time-series data from the AD converters are subjected to Fourier Transform by a butterfly operation technique. The digitizer apparatus further includes a window function multiplier for determining a coefficient based on a phase error, and a butterfly operation unit for performing a butterfly operation by inserting a phase correction coefficient.