Abstract: A method for improving the execution speed of compare operations in graphic software functions running on a RISC processor. A branch instruction in a software function comparing the value of two variables is replaced with an inline compare instruction that encodes the result of the compare into a third variable using an arithmetic shift-left instruction. An inline choice instruction selects the value of one of the two variables using the value of the third variable as a mask. The inline compare and an inline choice instructions reduce processor stalls during execution.

Abstract: Method and system aspects properly enable and disable a function in a peripheral device. In a system aspect, the system includes a processing system, and a control mechanism within the peripheral device and coupled to the processing system, the control mechanism controlling enabling and disabling of a function in the peripheral device. The control mechanism further includes a decoder coupled to the processing system, and a counter coupled to the decoder. In a method aspect, the method includes receiving first and second control signals at a control mechanism in the peripheral device from at least one component in the processing system, and maintaining a state of the peripheral device at a predetermined level according to a value of the control mechanism, wherein the first and second control signals alter the value of the control mechanism.

Abstract: A sleep mode controller, useful for an electronic device such as a computer, can supply multiple clocks with appropriate synchronization and which is capable of dynamic speed switching. The device provides clock signals at various speeds and relationships which can in turn be used to support various functions of the electronic device. The sleep mode controller can be activated and smoothly transition various clock signals from one time domain to a second time domain, each of which has predetermined speeds and clock-signal relationships. Dynamic speed switching is used to reset timing (bus and processor clock) sensitive elements such that computer machine speed (bus and processor clock frequencies) can be changed dynamically without interruption of I/O services or general OS and application level functions.

Abstract: An apparatus for ensuring that creating the necessary control signalling of multiple implementations of the power ramp operation of a radio transmitter as described. The apparatus provides for a flexible ramp up and ramp down to a plurality of sections of a radio in a wireless local area network. The apparatus includes a plurality of control pins, and a user programmable device for configuring the control pins to provide programmable ramp up and ramp down signals to the plurality of sections of the radio. Accordingly, it is possible to program the ramp up and ramp down function of the radio. The apparatus also ensures that a radio in a wireless local area network does not inappropriately enter into an active state. The apparatus utilizes the user programmable device to configure the control pins to ensure that a signal and its complementary signal are both provided to the radio to ensure that the appropriate signal is utilized to activate the radio.

Abstract: A fencing system for a small systems computer interface (SCSI) bus based multiprocessor system having a first processor, a second processor, a peripheral device and a SCSI bus for connecting the first and the second processors to the peripheral device. The inventive fencing system is connected to the SCSI bus and includes a system controller for generating a fencing signal and a device address. A fence control circuit is included for receiving the fencing signal and the device address and for disabling communication between the first processor and the peripheral device in response thereto. In a particular embodiment, a differential driver and receiver are provided on each line of the SCSI bus. The fencing system disables each driver and receiver for the processor to be fenced effectively isolating it from the peripheral device or its controller. Hence, the invention provides a system and technique for fencing nonproprietary i.e., SCSI based clusters of processors.

Abstract: A method for increasing the speed of a Z-buffer process. The method operates on the observation that groups of points in a scan-line of a polygon are either all visible or all obscured by existing points in the frame buffer. The method processes visible points separately from obscured points. The method only calculates changes in point intensity for the groups of visible points. In addition, the termination of the two separate processes is controlled by placing sentinels at the edge of each scan-line of the polygon so that the comparison of the point's z-values also act as a check for process termination.

Abstract: A method and system for highlighting typography along a geometric path by a graphics system that includes a dashing feature is disclosed. The dashing feature is first used to determine the shape of the geometric path along a segment on which the typography is positioned. The dashing feature is then used to dash the segment with a non-repeating pattern. After dashing, the segment is outset from the geometric path to create an upper path, and inset from the geometric path to create a lower path. The method and system further includes connecting the upper and lower paths to create a new shape, and then filling-in the new shape to provide a field of continuous highlighting.

Abstract: A method for reducing dispatch stalls includes tracking allocation and deallocation of real rename buffers for instructions dispatched by a dispatch unit, and providing at least one virtual rename buffer for allocation of an instruction when the real rename buffers have been allocated. The method further includes tagging the instruction allocated to the at least one virtual rename buffer with a rename buffer busy signal, wherein the rename buffer busy signal indicates to an execution unit that the instruction cannot be completed. An efficient system for utilization of rename buffers in a superscalar processor includes a plurality of rename buffers, a dispatch unit coupled to the plurality of rename buffers, and an allocation/deallocation table coupled to the dispatch unit and the plurality of rename buffers. Further, the table includes a plurality of real rename buffer slots and at least one virtual rename buffer slot.

Abstract: A system and method for improving the performance of a processor that emulates a guest instruction where the guest instruction includes a first and second operand. The first operand is stored in a general purpose register, and the second operand is stored in a special-purpose register. The method and system provides a host instruction that performs an operation using the first operand and the second operand without moving the second operand from the special-purpose register into the general purpose register. This reduces the number of instructions in the semantic routines necessary to operate on immediate data from guest instructions and increases emulation performance.

Abstract: A method for detecting bypass error conditions in a load/store unit of a superscalar processor includes determining whether a load instruction has executed out-of-order with respect to an executing store instruction when a real address to a word boundary of the load instruction and a real address to a word boundary of the executing store instruction match, and identifying a bypass error condition for the load instruction when the load instruction has executed out-of-order with respect to the executing store instruction. In a system aspect, the system includes a load queue, detection logic, and completion logic. The load queue includes a real page number buffer for storing a real address to a word boundary for each executed load instruction. The detection logic compares real addresses to a word boundary for a load instruction against an executing store instruction and compares a program order of the load instruction and the executing store instruction when the real addresses to a word boundary match.

Abstract: A method for sensing the content of a FLASH memory cell, and a new FLASH memory cell structure that is suitable for use with this new sensing scheme. In a first aspect, a semiconductor memory cell comprises a lightly doped n-region including a channel region; a first insulating layer overlying portions of said n-region; a floating gate overlying said first insulating layer; a second insulating layer overlying said floating gate; and a control gate overlying second insulating layer.

Abstract: A method and system for reconstructing a relationship among events in a processing system, the processing system including at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least one PMC, includes controlling a mode of updating the at least one PMC through a bit set within the at least one MMCR, the bit set having a plurality of logic levels. Further included are determining if the bit set is at a first logic level, and placing the at least one PMC in a history mode if the bit set is at the first logic level.

Abstract: A method for identifying bottlenecks within a processing system, the processing system including a plurality of performance monitor counters (PMCs) and at least one monitor mode control register (MMCR) to configure the operations of at least one of the PMCs, includes, for a predetermined sampling period, counting a number of cycles that a dispatch unit is stalled, counting a number of cycles that each of a plurality of execution units is stalled, counting a number of cycles that a load/store unit is stalled, and counting a number of cycles that a completion unit is stalled. The counting in the units is performed to identify the relative effect of stalls occurring within each unit during processing to produce an overview of relative effect of the stalling of each unit on the total system bottleneck conditions.

Abstract: A system and method for a dynamic random access memory. The dynamic random access memory further comprises a memory block and a plurality of data lines. The memory block further comprises a plurality of memory cells. The plurality of memory cells are arranged into a plurality of rows and a plurality of columns. The plurality of data lines is proportional to the plurality of columns. Each of the plurality of data lines is substantially parallel to the plurality of columns.

Abstract: A method and system for monitoring performance of a processing system, the processing system including a plurality of performance monitor counters (PMCs) and at least one monitor mode control register (MMCR) to configure the operations of at least one of the PMCs, includes identifying misaligned data items, and determining a performance penalty of misaligned data accesses during a predetermined sampling period.

Abstract: A garment for holding reading material includes a pocket member. The garment also includes an attachment portion which attaches to the pocket member for retaining the reading material to the pocket member. In a first aspect, the attachment portion is a string attached to a cover portion which covers a book. In a second aspect, a back cover of a book is sewn onto the garment.

Abstract: A method and system for automatically focusing an image within a still camera is disclosed. The method and system comprises providing initial focus and exposure values of the image, calculating an exposure setting for the image, and determining a plurality of focus zones for the image. The method and system includes moving the lens through the plurality of focus zones of the image to obtain exposure and focus information about the image. Through a method and system in accordance with the present invention, a digital still camera can produce a three-dimensional like data set of a scene.

Abstract: A method and system for reducing the dispatch latency of instructions of a processor provides for reordering the instructions in a predetermined format before the instructions enter the cache. The method and system also stores information in the cache relating to the reordering of the instructions. The reordered instructions are then provided to the appropriate execution units based upon the predetermined format. With this system, a dispatch buffer is not required when sending the instructions to the cache.

Abstract: A system and method for supporting constant bit rate encoded MPEG-2 transport over local Asynchronous Transfer Mode (ATM) networks. The present invention encapsulates constant bit rate encoded MPEG-2 transport packets, which are 188 bytes is size, in an ATM AAL-5 Protocol Data Unit (PDU), which is 65,535 bytes in size. The method and system includes inserting a plurality of MPEG-2 transport packets into a single AAL-5 PDU, inserting a segment trailer into the ATM packet after every two MPEG packets, and then inserting an ATM trailer at the end of the ATM packet. In a preferred embodiment, 10 or 12 MPEG-2 transport packets are packed into one AAL-5 PDU to yield a throughput 70.36 and 78.98 Mbits/sec, respectively, thereby supporting fast forward and backward playing of MPEG-2 movies via ATM networks.

Abstract: The present invention provides a method and system for using hardware to assist software in emulating the guest instructions. The method and system comprises an emulation assist unit (EAU) which efficiently maps a guest instruction to a unique tag, an index, and an address of the corresponding semantic routine. The index determines where in a cache a plurality of tags are stored. A separate cache within the EAU stores each tag in association with the address the first time the corresponding guest instruction is emulated. Thus, the emulation assist unit also dynamically responds to the set of guest instructions being emulated. The first time a guest instruction is emulated, the EAU determines the address and stores the address in the cache in association with the tag. When the guest instruction is emulated again, the EAU uses the tag to access the stored addresses of the corresponding semantic routine.