Abstract: A system and method for improving arbitration of a plurality of events that may require access to a cache is disclosed. In a first aspect, the method and system provide dynamic arbitration. The first aspect comprises first logic for determining whether at least one of the plurality of events requires access to the cache and for outputting at least one signal in response thereto. Second logic coupled to the first logic determines the priority of each of the plurality of events in response to the at least one signal and outputs a second signal specifying the priority of each event. Third logic coupled to the second logic grants access to the cache in response to the second signal. A second aspect of the method and system provides user programmable arbitration. The second aspect comprises a storage unit which allows the user to input information indicating the priority of at least one of the plurality of events and outputs a first signal in response to the information.

Abstract: A microprocessor architecture including a first cache memory disposed on-chip for storing data along with an associated on-chip tag memory. A second memory is provided on-chip for storing data in a first mode of operation and for storing tags relating to the contents of a second cache memory in a second mode of operation. The mode of operation is set by control logic. The mode is selected by setting a bit in a mode control register. When the bit is set, the control logic changes the system from a first mode in which the second memory serves as additional on-chip cache memory to a second mode in which the second memory stores tags for an external level 2 cache memory. The invention provides a flexible cache structure in which increased on-chip cache is provided or tag memory area is provided for an off-chip level 2 cache.

Abstract: A distributed completion control system for a microprocessor is disclosed. The system comprises a plurality of dispatch units, each of the dispatch units further comprises a dispatch queue responsive to a fetched address for receiving instructions; a plurality of control dependent tags; and means for indicating that the control dependent tags have been assigned to the appropriate instructions. The system further includes a plurality of execution units for receiving the instructions and the control dependent tags.

Abstract: A removable auxiliary electrical component for an electrical device that can be removed when the electrical device is powered is disclosed. The removable axillary electrical component includes a module located on an exterior portion of an electrical product. The removable axillary electrical component also includes a guard member connected to an electrical product. The electrical product includes an electrical contact portion connected to a power source of the electrical product, and a housing member containing a first electrical portion of the module. The electrical portion includes a second contact portion, the second contact portion is used for mateably engaging the first contact portion. The housing portion also includes a snap member for removable engagement with the exterior portion of the electrical product.

Abstract: A cable television (CTV) system having an ad-insertion apparatus for automatically inserting commercial segments into program material under the control of cue tones transmitted by the program source. The system includes apparatus for normalizing the audio signal levels of the program and commercial materials so that the audio portion of the output signal being transmitted to subscribers will have a relatively uniform loudness. The same concept may be applied to video signals. Additionally, signals coming from several channels may be normalized with respect to each other using the same technique. One aspect involves normalization of the audio level of the commercial, based on measured levels of the program audio preceding the advertisement. In other variations, the program audio level is adjusted to match a preset audio level of an advertisement. In another aspect of the invention, the audio level adjustment is achieved by monitoring the deviation of an audio modulator.

Abstract: A microphone including an infrared switch circuit is disclosed. The infrared switch circuit includes an infrared detector for detecting a reflection of an infrared signal off an object such as a human body, and producing an electrical signal. The circuit also includes an amplifier for amplifying the electrical signal and a comparator for determining if the amplified electrical signal is above a predetermined threshold. The switching finally includes a audio switching network for providing the amplified signal as an audio signal if the amplified signal is above a predetermined threshold. The circuit also includes power conservation techniques to improve performance.

Abstract: A chemical mechanical polisher is provided comprising multiple polish platens to sequentially remove any fixed amount of oxide or metal on a semiconductor wafer. Each polish platen polishes a fraction of the total oxide removed. Total oxide removal is achieved after completing polishing on all available polish platens assigned for polishing. Reduced oxide removed enables a high oxide removal rate on each polish platen, thus reducing polish time. Sequential polishing on multiple polish platens reduces polish time especially for high oxide removal in the range greater than 0.5 micrometer to greater than 1 micrometer. A higher polish rate and shorter polish time results in shorter polish pad conditioning time. Multiple polish platens coupled with more than one consecutive wafer-carrier head, each following the previous wafer-carrier head in completing sequential polishing, improves machine throughput by eliminating machine idle time caused by events other than actual oxide or metal polishing.

Abstract: The present invention is directed toward a novel type of FLASH EEPROM cell that is highly scalable in size, easy to fabricate, reliable and capable of in-system programmability. The semiconductor memory cell comprises a lightly doped n- region including a channel region, a first insulating layer overlying portions of said n- region, and a floating gate overlying said first insulating layer. The cell further includes a second insulating layer overlying said floating gate and a control gate overlying second insulating layer.

Abstract: Apparatus for control of a moving vehicle is disclosed. The apparatus comprises an electronically-activated traction control system for control of traction of the wheels of the vehicle, with computer software for control of the system, a receiver for receiving an electronic signal and which is capable of being activated from a remote location and a controller implementing the computer software within the traction control system which is capable of being activated by a signal transmitted to the receiver. On receipt of the electronic signal, a reduction in the speed of the motor vehicle is effected by activation of the traction control system.

Abstract: A plurality of transistors according to the present invention formed on a semiconductor wafer including a plurality of non-ESD transistors, the plurality of non-ESD transistors including spacer regions and impurity implant regions encroaching the spacer regions, and a plurality of ESD transistors, the plurality of ESD transistors formed at a predetermined angular offset from the non-ESD transistors. Further, the plurality of ESD transistors include the spacer regions and impurity implant regions encroaching the spacer regions further than the impurity implant regions of the non-ESD transistors.

Abstract: A method is provided for forming metal interconnect structures which resists the formation of pile-ups caused by electromigration. Each metal interconnect structure includes an aluminum interconnect sandwiched between two refractory metal layers. The method of the present invention involves forming a layer of aluminum intermetallic alloy on the sidewalls of the aluminum interconnects. The layer of aluminum intermetallic alloy provides reinforcement for the sidewalls. The layer of aluminum intermetallic alloy comprises aluminum-refractory metal alloy. The aluminum-refractory metal alloy is formed by reacting the exposed aluminum on the sidewalls with refractory metal-containing precursor material. After the formation of the layer of aluminum intermetallic alloy the sidewalls of the aluminum interconnects, the formation of pile-ups will be suppressed. Thus, the lifetime of the aluminum interconnects is extended.

Abstract: A timing driven placement system and method for designing an integrated circuit. The inventive method includes the steps of identifying a plurality of nets having blocks of circuit components connected by conductive elements and assigning weights to the nets in proportion to timing and resistive-capacitive (RC) effects therein. In the preferred embodiment, the weights are used by a conventional placement program to obtain the final placements.

Abstract: A digital phase lock loop and system for data extraction and clock recovery of Ethernet data reduces power consumption, area, and noise sensitivity. In one aspect, a digital phase lock loop (PLL) includes a data extraction and end of transmission delimiter (ETD) circuit, an edge detection comparator coupled to the data extraction and ETD circuit, an up/down counter coupled to the edge detection comparator, and a phase adjustment oscillator coupled to the counter and to the data extraction and ETD circuit for producing phase adjustments in a reference clock signal in accordance with shifts in the frequency of the data. In a system aspect of the present invention, the system receives the data in a digital PLL circuit, and adjusts a phase of a reference clock and a sample clock to track transitions in the data through the digital PLL.

Abstract: A system and method for performing an emulation context switch save and restore in a processor that executes host applications and emulates guest applications. The processor includes an operating system and a first register that is saved and restored by the operating system during a host application context switch. The method and system comprises renaming the special-purpose register to the first register when emulating guest applications. When an emulation context switch occurs, a context save and restore of the special-purpose register is performed through the first register without operating system modification.

Abstract: A method for improved recursive pitch prediction includes providing a search window for pitch estimates based upon a previously computed pitch, computing pitch estimates for the search window, and determining an optimal pitch from the pitch estimates within the search window for a first predetermined number of frames. The method further includes expanding the search window to a full pitch window after the first predetermined number of frames, and calculating pitch estimates for the full pitch window for a second predetermined number of frames.A system for improved recursive pitch prediction includes a speech generator of speech signals, and a central processing unit coupled to the speech generator.

Abstract: A method and system eliminates visible quantizing artifacts in a digital image. The present invention eliminates visible artifacts by determining a function descriptive of a noise model for an input source of image data, utilizing a critical noise/quantizing factor in conjunction with the noise model function to determine a quantization function, and deriving optimum coding for the image data from the quantization function to produce digital image data lacking visible quantization artifacts. The critical noise/quantizing factor is a constant value found to be a value of 3/8. The present invention further includes deriving inverse coding for the optimum coding to allow processing of the digital image.

Abstract: A system and method for automatically refreshing a dynamic random access memory is disclosed. The system comprises a timer, a trigger, and refresh generation means coupled to the timer and the trigger. The timer provides a first refresh rate. The first refresh rate is a required number of refreshes for a particular interval of time. The trigger provides a trigger signal. The trigger signal is a periodic signal. The refresh generation provide a plurality of refreshes at a second refresh rate in response to the trigger signal. The system functions such that the second refresh rate adapts to the first refresh rate.

Abstract: A FLASH EPROM cell in accordance with the present invention is disclosed in which the erasure is accomplished under a constant electric field. The FLASH EPROM cell includes a semiconductor device including a source, a drain and a gate and a constant current circuit coupled to the source. The constant current circuit ensures that a constant field is applied to the tunneling oxide of the FLASH EPROM cell during erasure thereof. In so doing, the FLASH EPROM cell can be erased with a minimum of stress to the device. In addition, the FLASH EPROM cell of the present invention can be used with various power supplies without affecting the characteristics thereof. Finally, through the FLASH EPROM cell of the present invention, the short channel effect associated with smaller device sizes can be substantially reduced.

Abstract: A method and system for fast calculation of the sticky bit and a function of the guard bit is disclosed. A first aspect of the method and system provides a fast calculation of the sticky bit. A second aspect provides a fast calculation of a function of the guard bit. Both aspects comprise means for providing an intermediate result of a floating point mathematical operation involving at least a first and a second operand and means for providing a mask indicating a position of a leading one in a mantissa of the intermediate result. In the first aspect, means for aligning a first bit of the mask to an (n+2)nd bit of the intermediate result, where n is the number of bits in a mantissa of the first or second operand, are coupled to the intermediate result providing means. In the second aspect, means for aligning a first bit of the mask to an (n+1)st bit of the intermediate result are coupled to the intermediate result providing means.

Abstract: A system and method for detecting and gracefully recovering from a peripheral device fault has been disclosed. The method detects whether a peripheral device has suffered from a peripheral device fault. Where the peripheral device fault has occurred, the method determines whether any of a plurality of processes executable by the peripheral device is currently being executed by the peripheral device. The plurality of processes comprises those process which could result in significant loss of data, loss of connection to a network or adversely affect the performance of the peripheral device if the peripheral device is reset during execution of any of the plurality of processes. If none of the plurality of processes is being executed by the peripheral device, the method automatically resets the peripheral device. According to the method and system disclosed, peripheral devices can be made to recover from faults without user intervention, without loss of connection to any networks, and with minimal loss of data.