Patents Represented by Law Firm Schneck & McHugh
  • Patent number: 5086325
    Abstract: An EEPROM design featuring narrow linear electrodes including a source, a drain, a thin oxide, channel and floating gate. A pair of linear, opposed field oxide barrier walls form widthwise boundaries of the active structure which can be very closely spaced. The drain electrode, implanted in the substrate, abuts both opposed field oxide lateral walls, but does not extend under either wall. The source, drain and channel are formed in a single implant followed by diffusion after the field oxide barrier walls are formed, but prior to formation of the floating gate. All abut opposed field oxide walls in a stripe design. A control gate is disposed over the floating gate. The combination of opposed field oxide barrier walls, a stripe electrode design, and single step implant for electrode formation results in a very compact cell, utilizing a simplified EEPROM process.
    Type: Grant
    Filed: November 21, 1990
    Date of Patent: February 4, 1992
    Assignee: Atmel Corporation
    Inventors: Steven J. Schumann, James C. Hu
  • Patent number: 5085362
    Abstract: An alignment apparatus for use in sealing of a package lid to a base of an integrated circuit package. A fabrication boat for leadless chip carriers includes a plurality of arrays of upwardly extending fingers disposed to secure a base of a leadless chip carrier. An alignment member is slidably fit over the carrier base and the upwardly extending fingers. Each alignment member includes shoulders, each shoulder having a lower vertical surface in contact with the carrier base and having a horizontal surface resting upon the carrier base. Upper vertical surfaces of the shoulders are spaced apart to slidably receive a package lid for alignment with the base. The package lids are held within the alignment member primarily by gravitational force.
    Type: Grant
    Filed: January 16, 1991
    Date of Patent: February 4, 1992
    Assignee: Atmel Corporation
    Inventors: Jack Art, Douglas J. Levad
  • Patent number: 5084629
    Abstract: An apparatus for detecting and counting particles in a gas stream flowing at a preselected rate, wherein the apparatus includes a multi-tier inlet manifold and a plurality of sensors. The inlet manifold divides an aggregate sample flow into a plurality of substantially identical partial sample flows. Each partial sample flow enters one of the functionally duplicative sensors and is intersected by an incident beam to define a view volume. Particles contained within the partial sample flows scatter light as the particles pass through the view volume. The scattered light is directed to a photodetector which provides a signal having characteristics corresponding to the sensed light. Particle detection in each view volume is operationally independent of the others, but the information is combined to provide a total particle count of the aggregate sample flow.
    Type: Grant
    Filed: May 7, 1990
    Date of Patent: January 28, 1992
    Assignee: Met One, Inc.
    Inventor: Louis J. Petralli
  • Patent number: 5083035
    Abstract: A particle imager and method for imaging particles on surfaces of substrates. A surface is raster scanned by a collimated light beam and particles on the surface are detected by the scattered light caused by the particles. During a scan path the intensity of the scattered light is measured forming intensity traces and location addresses for the detected particles. Data from each scan path is stored in memory. The imager is pre-calibrated with a test wafer having light scattering marker points spaced at known positions thereon. Scanning the test wafer, a clock measures time elapsed from a start position to each marker point. The corresponding elapsed times and known address locations are stored in memory for reference during data collection.
    Type: Grant
    Filed: July 17, 1990
    Date of Patent: January 21, 1992
    Assignee: Tencor Instruments
    Inventors: Jiri Pecen, Kenneth P. Gross, Brian Leslie, George Kren
  • Patent number: 5081054
    Abstract: An electrically programmable and electrically erasable MOS memory device having a floating gate which is separated from the semiconductor substrate by a thin oxide layer, the memory device also having an impurity implant in the substrate which extends under an edge of the floating gate beneath the thin oxide layer. In one embodiment the thin oxide layer underlies the entire floating gate while in another embodiment only a portion of a small thin side window extends under the floating gate's edge. Also disclosed is a fabrication process in which the one embodiment is formed by first forming the floating gate over the thin oxide layer and then implanting the impurity near an edge of the floating gate. Later steps with heating cause the implanted impurity to diffuse under the floating gate edge. An alternative process first forms a window in the gate oxide layer and implants the impurity through the window.
    Type: Grant
    Filed: February 5, 1991
    Date of Patent: January 14, 1992
    Assignee: Atmel Corporation
    Inventors: Tsung-Ching Wu, Geeng-Chuan Chern
  • Patent number: 5079835
    Abstract: An integrated circuit package and method of making the package which allows an integrated circuit die to be bonded to a substrate without need of a carrier. The integrated circuit die has opposed active and passive surfaces and has lateral surfaces. An electrically insulative layer of material is deposited on the passive and lateral surfaces. A metal mask is formed to cover the active surface and the coated lateral surfaces. The metal mask includes slots which extend up the lateral surfaces and onto the active surface. The array of slots corresponds to an array of input/output contact pads on the active side. Metal is sputtered into the slots, whereafter the mask is removed to provide L-shaped conductive traces from the contact pads along the active and lateral sides. The assembly can then be rested on a substrate on the passive surface and the L-shaped traces bonded to contact pads on the substrate. The assembly allows testing at the die level.
    Type: Grant
    Filed: October 12, 1990
    Date of Patent: January 14, 1992
    Assignee: Atmel Corporation
    Inventor: Man K. Lam
  • Patent number: 5078492
    Abstract: A patterned wafer for testing an optical scanner. The wafer has standard size light scattering features, such as pits, distributed in aligned groups arranged in annular bands about a concentric center. Empty annular bands separate the feature containing annular bands. The empty bands simulate wafer edges for various size wafers. In this manner, wafer edges may be excluded in a particle count for a predetermined size wafer. Apparent size variations in multiple scans indicate misalignments relative to the scan center.
    Type: Grant
    Filed: June 17, 1991
    Date of Patent: January 7, 1992
    Assignee: VLSI Standards, Inc.
    Inventor: Bradley W. Scheer
  • Patent number: 5079451
    Abstract: A programmable logic device having a programmable AND (product term) array formed with input terms on both global and local busses and with both global and local product term lines. Each macrocell of the device, whether as input/output macrocell connected to an I/O pin or a buried macrocell providing only feedback, connects to and receives an inputs both global and local product terms. In one embodiment, global product terms are connectable to the global bus and to a local bus corresponding to a particular group or quadrant of macrocells. Local product terms are only connectable to that local bus, and thus only a fraction of the terms available to the global product terms. In an alternate embodiment, global product terms are connectable to the global bus and to a set of local busses which is a prope subset of all of the local busses. Local product terms are connectable only to the particular local bus assigned to a particular group or quadrant of macrocells and to a fraction of the terms on the global bus.
    Type: Grant
    Filed: December 13, 1990
    Date of Patent: January 7, 1992
    Assignee: Atmel Corporation
    Inventors: Keith H. Gudger, Geoffrey S. Gongwer
  • Patent number: 5077690
    Abstract: A memory system in which the input/output circuitry can be tested independently from the storage cells and decoder therein by permitting a write operation, with information at the memory inputs being provided to the memory outputs as well as to the storage cells.
    Type: Grant
    Filed: August 9, 1989
    Date of Patent: December 31, 1991
    Assignee: Atmel Corporation
    Inventor: Paul J. Smith
  • Patent number: 5076692
    Abstract: A method and apparatus for predicting the number of contaminant particles in circuit area of a patterned semiconductor wafer having a number of reflective circuit areas. The method includes forming on a wafer in specified areas, a grating test pattern, such as a line grating. The grating patterns are formed at the same time and in the same manner that repetitive circuit patterns are formed on the wafer. The wafer is then scanned by a light beam. Since the diffraction pattern caused by the grating test patterns is known, it is possible to detect when the light beam is scanning one of the known grating patterns. The diffraction pattern may be inspected for fabrication derived variations. In response to detecting a known grating pattern, a detection mechanism is activated. Since the diffraction pattern is known it may be spatially separated. In this way only light scattered by particles or defects in the pattern are collected and detected.
    Type: Grant
    Filed: May 31, 1990
    Date of Patent: December 31, 1991
    Assignee: Tencor Instruments
    Inventors: Armand P. Neukermans, Peter C. Jann, Ralph Wolf, David Wolze, Stanley Stokowski
  • Patent number: 5077809
    Abstract: A technique for optical recognition of a designated character, which forms alternating dark and light bands from an analysis of as many as seven sub-regions of the character. Only the dark-and-light sequence of bands, not the relative or absolute sizes of these bands, is used to identify the character. The dark-and-light sequences found for the designated character are each compared with the corresponding sequences for a group of candidate characters available in a data base. Using a binary decision tree analysis, one or more candidate characters is identified whose sequences match the corresponding sequences for the designated character. If more than one candidate character is thus identified, any of seven additional processing techniques can be used to reduce the number of surviving candidate characters to a single character.
    Type: Grant
    Filed: May 30, 1989
    Date of Patent: December 31, 1991
    Inventor: Farshad Ghazizadeh
  • Patent number: 5069154
    Abstract: A safety system associated with an engine of a marine vessel wherein the safety system includes a blower, a control unit, and a plurality of sensors. An intake pressure detection device is coupled to the intake manifold of the engine for the detection of pressure at the intake manifold. A sensor is coupled to the engine to monitor oil pressure and, along with the intake pressure detection device, transmits a signal to the control unit, with the signals each having a characteristic corresponding to the respective engine pressure. Detection of an engine pressure associated with engine idling or low cruise operation causes the control unit to activate the blower. The safety system includes interactive heat sensors and vapor sensors to monitor the atmosphere in an engine compartment. Detection of a volatile environment activates the blower and triggers both an audio and a visual warning.
    Type: Grant
    Filed: July 27, 1990
    Date of Patent: December 3, 1991
    Inventor: John A. Carter
  • Patent number: 5066992
    Abstract: An electrically programmable and electrically erasable MOS memory device having a floating gate which is separated from the semiconductor substrate by a thin oxide layer, the memory device also having an impurity implant in the substrate which extends under an edge of the floating gate beneath the thin oxide layer. In one embodiment the thin oxide layer underlies the entire floating gate while in another embodiment only a portion of a small thin side window extends under the floating gate's edge. Also disclosed is a fabrication process in which the one embodiment is formed by first forming the floating gate over the thin oxide layer and then implanting the impurity near an edge of the floating gate. Later steps with heating cause the implanted impurity to diffuse under the floating gate edge. An alternative process first forms a window in the gate oxide layer and implants the impurity through the window.
    Type: Grant
    Filed: October 29, 1990
    Date of Patent: November 19, 1991
    Assignee: Atmel Corporation
    Inventors: Tsung-Ching Wu, Geeng-Chuan Chern
  • Patent number: 5065149
    Abstract: Method and apparatus for providing high resolution images for static display of document pages that are scanned in through a document scanner at high resolution, with reduced bandwidth requirements. In one embodiment, groups of four scanned image pixel values, each one bit in length, are reduced to a single two-bit pixel value that determines a pixel value for a display image pixel; and selected displayed image pixel values are periodically varied between the original displayed image pixel value and an alternative pixel value to restore the perception of high resolution available in the scanned image.
    Type: Grant
    Filed: November 9, 1989
    Date of Patent: November 12, 1991
    Assignee: Document Technologies, Inc.
    Inventors: Robert M. Marsh, Timothy J. Hill, Mark Potts
  • Patent number: 5065045
    Abstract: A multistage voltage comparator having plural transfer stages between successive comparator stages. Each transfer stage includes capacitors connected between the outputs of one stage and the inputs of the next stage. The capacitors are also connected to a reference voltage line via MOS transistor switches. The switches are characterized by progressively slower turn-off times for each successive transfer stage so that turn off is sequential. The comparator is a differential amplifier with two complementary inputs and outputs. The complementary outputs of the final stage are loaded into a latch and then transferred to an RS flip-flop providing a digital logic output representative of at least a quantization step difference in the inputs to the first comparator stage.
    Type: Grant
    Filed: October 4, 1990
    Date of Patent: November 12, 1991
    Assignee: Atmel Corporation
    Inventor: Tsung Dai Mok
  • Patent number: 5065401
    Abstract: A method of driving a multimode laser diode has pulse circuitry providing a sequence of drive current pulses to the laser and modulation circuitry superimposing a modulation current upon the drive current pulses. When the modulation amplitude and rate are sufficiently great, rapid switching of transverse modes of laser operation is induced during each laser pulse. The effect of many different modes is averaged out so that the observed light output, even in a high power apertured system, is stable both within a single pulse and from one pulse to the next.
    Type: Grant
    Filed: February 26, 1991
    Date of Patent: November 12, 1991
    Assignee: Spectra Diode Laboratories, Inc.
    Inventors: Donald R. Scifres, John G. Endriz
  • Patent number: 5060370
    Abstract: A method of improving or modifying a fabricated circuit board having a circuit pattern of board traces etched thereon. First and second locations on the printed circuit board are identified for electrical connection of the two locations for the purpose of modifying the circuit board. A path is then selected from the first location to the second location generally without crossing of etched board traces. A metallic panel is provided and metal is removed from the panel to form a plurality of lay-flat traces in a configuration to match the selected path. Preferably, the lay-flat traces are plated with copper and then tin or solder. An overcoating of an insulating material, such as photo-imageable solder mask, is then applied. One of the lay-flat traces can then be removed from the panel and installed on the board to follow the selected path from the first location to the second location. Annular pads at the opposed ends of the lay-flat trace are soldered to the two locations.
    Type: Grant
    Filed: October 15, 1990
    Date of Patent: October 29, 1991
    Inventors: James W. Scales, Jr., Walter L. Marks
  • Patent number: 5056082
    Abstract: A spindle clamp for removably supporting a data disk wherein the clamp has a spindle adapted for rotation about a vertical axis. The top of the spindle is stepped, having an inner raised surface, an intermediate gap-forming surface and an outer disk-seating surface. A segmented annular jaw assembly rests atop the raised surface and forms an annulus having an outer diameter less than the inside diameter of the data disk. The radially inward portion of the jaw assembly has an inverted and truncated conical bearing surface in frictional contact with a conforming wedge surface of a cam member. Downward displacement of the cam member causes the wedge surface to move the individual segments of the jaw assembly in a radially outward direction. The cam member is moved pneumatically from a disk-releasing position to a lower disk-clamping position that positions the edges of the individual segments of the jaw assembly above the data disk.
    Type: Grant
    Filed: June 12, 1989
    Date of Patent: October 8, 1991
    Inventor: Donald L. Ekhoff
  • Patent number: 5047619
    Abstract: A data storage medium having a pattern representing data bits arranged in a plurality of interlocked triangularly shaped tracks. The medium may be a prerecorded optical storage material having a set of optically contrasting marks arranged in the tracks. The track width increases from a start point to an end point at a constant rate that depends on the maximum allowable angle of skew. The medium, which can be prerecorded with the pattern using exposure to actinic radiation through a like-patterned master, can have either a card, tape or drum format.
    Type: Grant
    Filed: July 18, 1989
    Date of Patent: September 10, 1991
    Assignee: Drexler Technology Corporation
    Inventor: Larry S. Zurbrick
  • Patent number: RE33722
    Abstract: An optical system producing bright light output for optical pumping, communications, illumination and the like in which one or more fiberoptic waveguides receive light from one or more diode lasers or diode laser bars and transmit the light to an output end where it is focused or collimated into a bright light image. The input end of the fiberoptic waveguide may be squashed into an elongated cross section so as to guide light emitted from an elongated light source such as a diode laser bar. The waveguides are preferably arranged at the output end into a tightly packed bundle where a lens or other optical means focuses or collimates the light. For diode laser bars much wider than 100 microns, a plurality of waveguides may be arranged in a line to receive the light, and then stacked at the output in a less elongated configuration. In this manner, light from many diode lasers or laser bars may be coupled through the bundle into the end of solid state laser medium.
    Type: Grant
    Filed: August 15, 1990
    Date of Patent: October 22, 1991
    Assignee: Spectra Diode Laboratories, Inc.
    Inventors: Donald R. Scifres, D. Philip Worland