Abstract: Generally speaking, systems, methods and media for automatically generating a role based access control model (RBAC) for an organizational environment with a role based access control system such as a hierarchical RBAC (HRBAC) system are disclosed. Embodiments may include a method for generating an RBAC model. Embodiments of the method may include accessing existing permissions granted to users of an organizational environment and analyzing the permissions to create permission characteristics. Embodiments of the method may also include performing cladistics analysis on the permission characteristics to determine role perspective relationships between individual users of the organizational environment. Embodiments of the method may also include generating an RBAC model based on the determined role perspective relationships between individual users of the organizational environment.

Abstract: Methods, systems, and media for enhancing persistence of a message are disclosed. Embodiments include hardware and/or software for storing of a message in an inbound queue, copying the message to a working queue prior to removing the message from the inbound queue, processing the message base upon the copy in the working queue, and storing a committed reply for the message in an outbound queue. Embodiments may also include a queue manager to persist the message and the committed reply after receipt of the message, to close or substantially close gaps in persistence. Several embodiments include a dispatcher that browses the inbound queue to listen for receipt of messages to process, copy the message to the working queue, and assign the message to a thread to perform processing associated with the message. Further embodiments include persistence functionality in middleware, alleviating the burden of persisting messages from applications like upperware.

Abstract: Vehicular situational awareness systems, method and arrangements are disclosed herein. In one embodiment digitized video can be acquired by a camera on a vehicle, and utilizing pixel differentiation at least one area of interest in the digitized video can be identified. The area of interest could be, for example, a group of pixels that represent another vehicle, a sign etc. Attribute information for the area of interest, such as size, movement etc. of an object, can be acquired and then it can be determined if the attribute information is significant enough or important enough to set an alarm condition and notify the driver.

Abstract: Generally speaking, systems, methods and media for managing an application usage metering system are disclosed. Embodiments of the method may include initiating discovery agents for one or more server resources and interrogating by the discovery agents the one or more server resources to discover a plurality of discrete server processes and associated discovery data for each process. Embodiments may also include collecting discovery data for the discovered discrete server processes in a centralized repository and mapping one or more of the processes to an application and a customer based on the collected discovery data. Further embodiments may also include performing an administrative function based on the mapped discrete server processes, such as generating a customer bill, generating a report based on the mapped discrete server processes, assigning a customer to a process, or changing a status of a discrete server process.

Abstract: In one embodiment a low voltage high performance memory system is disclosed. The system can include a bit cell, a first pass gate coupled to the bit cell to receive a write signal, a second pass gate coupled to the bit cell to receive the write signal, and an supply current controller to reduce current to at least a portion of the bit cell and to supply current to another portion of the cell in response to a write control signal and a data signal during a bit cell transition. Reducing the current to a portion of the bit cell and supplying current to another portion of the bit cell during transition can allow the bit cell to transition to a different state faster and can reduce the effects of device variations that manifest during low voltage operation. Other embodiments are also disclosed.

Abstract: Methods and arrangements to determine a value of an option dependent upon a stochastic variable are contemplated. One embodiment provides a method to determine a value of an option dependent upon a stochastic variable. The method may involve receiving a specification of permissible error for the determination and an error weight function, apportioning a permissible error among multiple time periods, and evolving the error weight function. The method may also include determining a value of the option at the time periods with the determination of a value for one or more times periods within the permissible error apportioned for the one or more time periods. The method may also include determining the value of the option, responsive to the determination of the values of the option at the plurality of time periods. In some embodiments, the stochastic variable may represent the price of one or more financial instruments.

Abstract: Methods for transitioning compression levels of a streaming image system are disclosed. One embodiment provides a method for transitioning compression levels between image frames in a streaming image system. Embodiments may include receiving by a smoothing module a request for a new compression level associated with an image frame. Embodiments may also generally include performing by the smoothing module a smoothing heuristic by generating a multi-frame smoothing routine based on an initial compression level, a target compression level, and a number of frames to achieve the target compression level. Embodiments may also include setting by the smoothing module the new compression level for the image frame based on the generated multi-frame smoothing routine. Further embodiments may include transmitting by the smoothing module an indication of the new compression level to a content encoder.

Abstract: Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.

Abstract: Methods for managing multiple sessions for a user on a portal are disclosed. More particularly, hardware and/or software for managing multiple user sessions with backend applications of a portal are disclosed. Embodiments include a portal having a client interaction module for interacting with a user and a portlet application module for interacting with a backend application on an application server. A further embodiment provides a session manager for retrieving application session data from an application session data cache and inserting it into a user request, and for removing application session data from a content transmission from a backend application. In some embodiments, a session data cache for storing portal session data and application session data is provided. The session data cache may store application session data for each session established by a user with backend applications.

Abstract: A forwarding table, in a network device such as a router, used to forward packets in a communications network includes indicia whose state determine whether information contained in the forwarding table or information contained in the header portion of a packet is to be used to forward the packet to the next hop (i.e. next point in the route).

Abstract: Embodiments may comprise a hybrid memory controller to facilitate accesses of more than on type of memory device, referred to generally hereafter as a hybrid memory device or hybrid cache device. The hybrid memory controller may include split logic to determine whether to split data of a write request into more than one portion and to store each portion in a different type of data storage device. For example, one embodiment comprises a hybrid memory controller to store data in both SRAM and DRAM devices. The SRAM and DRAM devices may include distinct circuits on a die, distinct dies within a chip, distinct chips on a memory module, distinct memory modules, or the like.

Abstract: Apparatuses, circuits, and methods to amplify signals with reduced jitter are disclosed. Embodiments generally comprise amplifiers coupled with apparatuses that adjust peak frequencies of the amplifiers to reduce jitter. In many system and apparatus embodiments, the frequency gain boosters receive one or more feedback signals derived from input signals applied to the amplifiers. The frequency gain boosters generally respond to the feedback signals by manipulating or controlling active loads coupled to the amplifiers. In controlling the active loads, the frequency gain boosters generally cause the active loads to peak at frequencies at or near the input signals, the result being attenuated jitter in an output signal of the amplifier.

Abstract: Methods and arrangements to insert values in hash tables are contemplated. Embodiments include transformations, code, state machines or other logic to insert values in a hash table stored in electronic memory by hashing a value to determine a home address of an entry in the hash table, the hash table having a plurality of entries, each entry comprising an address, a value, and a link. The embodiments may include determining whether there is a collision of the value with a value stored in the entry; inserting the value in the entry if there is no collision; and generating the addresses of further entries until an entry is found in which the value can be inserted if there is a collision. The embodiments may include generating a plurality of addresses of entries based upon the address of a previously generated entry.

Abstract: Methods for dynamic schema-based silicon IP analysis, qualification, data exchange, and integration are disclosed. Embodiments include determining a new resident schema associated with a function of a silicon IP design system that is different than a previous resident schema associated with a current view. Embodiments further include analyzing components of the new resident schema and parsing the current view and repository or IP database based on the new resident schema to extract pertinent data from the current view and the database and generating a new view by mapping the extracted data to the new resident schema where the new view includes viewable data associated with the function. Further embodiments may include presenting the generated new view to a user or storing the viewable data in a database. The new resident schema may be described in an XML or other appropriate schema language and notations.

Abstract: A system and method are described for performing security operations on network data. According to an exemplary embodiment, a system for performing security operations on network data includes memory and a data coprocessor configured to transfer data into and out of the memory. A plurality of processors are coupled to the memory and to the data coprocessor. Each processor is configured to perform, in parallel to one another, security operations on a portion of the data. The system includes a plurality of security coprocessors coupled to the memory. Each security coprocessor is coupled to a respective one of the processors and configured to assist the respective processor in performing security operations on the portion of the data.

Abstract: Systems, methods and media for a fast locking phase locked loop (FLPLL) are disclosed. A FLPLL apparatus can include a voltage controlled oscillator (VCO) coupled to a phase frequency detector and can also include a frequency divider as part of a feedback loop. The VCO can accept a pull up voltage and a control signal from the phase frequency detector and provide an output clock signal to circuits that need synchronization. Such a configuration can greatly reduce the time the PLL requires to go from a dormant state to a fully operational state. During this start up mode, a frequency detection module can be utilized to detect an output frequency of the voltage controlled oscillator and when the VCO output frequency is not as high as a reference frequency, the frequency detection module can disabled the feedback loop during this start-up mode.

Abstract: Methods for detecting outbound Nagling on a TCP network connection are disclosed. Embodiments may include creating by a sender computer one or more segments to be transmitted to a receiver computer and determining by the sender computer whether any of the one or more segments to be transmitted are small segments and determining whether a previously transmitted small segment is unacknowledged by the receiver computer. If the previously transmitted small segment is unacknowledged by the receiver computer and at least one of the segments to be transmitted is a small segment, embodiments may also include detecting by the sender computer a Nagling condition on the network connection. Further embodiments may include modifying a Nagle algorithm configuration of the network connection in response to the detected Nagling condition by turning off the Nagle algorithm or reducing a delayed acknowledgement timer for the network connection.

Abstract: Embodiments may include connectors with discharge elements integrated into the connectors to interconnect conductors of a cable to attenuate or discharge an electrostatic charge built up on the conductors. In some embodiments, the conductors are momentarily connected to ground as the connector couples with another connector to interconnect a cable with, e.g., a computer. In further embodiments, the discharge elements interconnect the conductors of a cable to redistribute an electrostatic charge and thereby minimize the impact of a discharge when the cable couples with an electronic system such as a computer. Another embodiment comprises a male connector with discharge elements, which ground conductors of the cable as the cable is being inserted into the connector. The discharge elements are pushed out of the way of the conductors as the conductors couple with the connector.

Abstract: Embodiments include systems and methods for processing Reliability, Availability and Serviceability (RAS) events in a computer system. Embodiments comprise processing critical events in a first portion of a Management Interrupt (MI) period. The MI period is chosen to be not greater than a maximum tolerable Operating System (OS) latency period. If time remains in a current MI period after processing critical events, the system then processes non-critical events during the time remaining in the current MI period. If at the end of the current MI period, some non-critical events remain to be processed, a subsequent MI period is scheduled to process the remaining non-critical events.

Abstract: A “digital data stream,” “binary sequence” or word can be generated by a logic circuit such as a processor and the sequence can be converted to a series of pulses such that the content of the sequence can be utilized to accurately control/drive a plurality of power transistors. Accordingly, a regulated voltage can be provided through such a data type output of a processor. Thus, a standard processor that executes data processing operations can provide a low level logic signal as a serial digital transmission, possibly a four bit word, and control a power supply without significant modification. To achieve such a conversion the processor can be capacitively coupled to a voltage level shifter and a delay module to provide a plurality of power transistor drive signals. The converter can be wholly integrated onto a processor or motherboard to eliminate devices and stand alone assemblies that are commonly required in data processing systems.