Abstract: Systems and methods for adaptively mapping system memory address bits into an instruction tag and an index into the cache are disclosed. More particularly, hardware and software are disclosed for observing collisions that occur for a given mapping of system memory bits into a tag and an index. Based on the observations, an optimal mapping may be determined that minimizes collisions.

Abstract: A method to improve polling accuracy in RFID systems is disclosed. Embodiments comprise receiving information from one or more tags by a tag reader, comparing the information from the tags to other information, and adding the tag to an inventory if the tag does not exist in the other information. While some embodiments compare the tag information from the tags to baseline inventories for other areas, some embodiments compare it to current inventories for the other areas or compare it to a combination of both inventories. Some embodiments involve polling RFID tags in storage containers.

Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.

Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.

Abstract: To provide a path controller capable of reducing path search time. A path controller 10 creates a logical tree LT having a plurality of member trees MT1 and MT2 within a routing table 52 at the time of initial setting. Direct tables DT1 and DT2 for the member trees MT1 and MT2 have the same DT entries (root). Unlike a conventional tree in which a single tree is constructed for the same root, since the present invention is such that the plurality of member trees are constructed for the same root, the number of nodes N passed through before reaching leaves L is reduced. At the time of path search, a plurality of search engines SE1 and SE2 search the member trees MT1 and MT2, respectively.

Abstract: An apparatus for inserting and/or removing a connector with a remote connector agent are disclosed. Embodiments may include a remote connector agent apparatus having a main body forming a connector cavity and one or more insertion snap pushers each having a lower surface. The insertion snap pushers may move outward during insertion of a connector into the connector cavity and move inward after insertion of the connector so that the snap pusher lower surfaces rest on a lip of the connector after insertion. Embodiments may also include a retraction holder ledge to support the lip of the inserted connector during retraction and a connector snap release actuator to pivot a snap of the inserted connector in response to a pulling force on the remote connector agent. The insertion snap pushers and the retraction holder ledge may have a float distance between them larger than the lip height.

Abstract: Embodiments include hardware and/or software for manufacturing a removable plate having a medium, to be integral to a casing for a processor-based device. Integrating the removable plate in or on the casing facilitates access to the medium and the data stored on the medium by providing storage in a location that is convenient and local to the processor-based device. The removable plate may include a first surface designed to cover a portion of the processor-based device and a second surface to provide access to the medium. The removable plate may also include any other types of media that can communicatively couple with the processor-based device directly, or indirectly through, e.g., a computer network.

Abstract: Methods and readable media for using relative positioning of items or components in a structure with dynamic ranges, such as an elastic I/O bus design for an Integrated Circuit (IC), are disclosed. Embodiments may include a user-defined type module having user-defined types representing relative instance positions within a structure. Embodiments may also include a translation helper module to receive information associated with a hierarchy and to return location information associated with the hierarchy and a translation module to translate between a specific location and a relative position of the instance based on one or more user-defined types and location information returned from the translation helper module to generate a list of translated results. Further embodiments of the translation module may include a relative position determiner to translate specific locations to relative positions and may also include a specific location determiner to translate relative positions to specific locations.

Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.

Abstract: A data packet switching node that temporarily stores data packets received from at least one source network adapter and transmits them to at least one destination network adapter comprises a data packet flow control system to control the data packet flow. The data packet flow control system comprises identifier to determine the at least one destination adapter of each received data packet. Then, flow control logic coupled to the storage allow computing a data packet flow value representing the traffic for the at least one destination adapter. The data packet flow value is transmitted simultaneously to the at least one source network adapter and to the at least one destination network adapter each time a data packet for the at least one destination network adapter is stored into the storage.

Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.

Abstract: Methods and arrangements to enhance photon emissions responsive to a signal within an integrated circuit (IC) for observability of signal states utilizing, e.g., picosecond imaging circuit analysis (PICA), are disclosed. Embodiments attach a beacon to the signal of interest and apply a voltage across the beacon to enhance photon emissions responsive to the signal of interest. The voltage is greater than the operable circuit voltage, Vdd, to enhance photon emissions with respect to intensity and energy. Thus, the photon emissions are more distinguishable from noise. In many embodiments, the beacon includes a transistor and, in several embodiments, the beacon includes an enablement device to enable and disable photon emissions from the beacon. Further, a PICA detector may capture photon emissions from the beacon and process the photons to generate time traces.

Abstract: Methods for detecting Nagling on a TCP network connection are disclosed. Embodiments may generally include a system with a Nagle detection threshold determiner for determining a Nagle detection threshold based on the network connection. The system may also generally include a Nagle detection module in communication with the Nagle detection threshold determiner for observing a small segment at a second time following an acknowledgement indicative of a Nagling condition at a first time, wherein the Nagle detection module also may detect a Nagling condition if the difference between the second time and the first time is less than or equal to the Nagle detection threshold. The system may be a receiver computer or a network computer. The system may also generate and transmit a notification of the Nagling condition, increment a Nagle monitor counter, or save an indication of the Nagling condition in a log.

Abstract: A system and method of protocol and frame classification in a system for data processing is disclosed, including, analyzing a portion of the, packet or frame according to predetermined tests, and storing characteristics of the packet for use in subsequent processing of the frame. The characteristics are preferably obtained with hardware, which does so quickly and in a uniform time period. The stored characteristics of the packet are then used by the network processing complexes in further processing of the frame. The processor is preconditioned with a starting instruction address or cede entry point and the location of the beginning of the layer 3 header as well as flags for the type of frame.

Abstract: Methods, systems, and media for reducing memory latency seen by processors by providing a measure of control over on-chip memory (OCM) management to software applications, implicitly and/or explicitly, via an operating system are contemplated. Many embodiments allow part of the OCM to be managed by software applications via an application program interface (API), and part managed by hardware. Thus, the software applications can provide guidance regarding address ranges to maintain close to the processor to reduce unnecessary latencies typically encountered when dependent upon cache controller policies. Several embodiments utilize a memory internal to the processor or on a processor node so the memory block used for this technique is referred to as OCM.

Abstract: Methods, systems, and media are disclosed for accessing one or more parts of an electronic document. In one embodiment, the method includes choosing, with a selecting device, the electronic document, and for receiving document utilization information for the electronic document. Further, the method includes displaying, on the computer, the electronic document and the document utilization information as an interactive graphical representation comprising a set of points, wherein each point in the set corresponds to both a different part of the electronic document and any of the document utilization information associated with the different part. Further still, the method includes selecting, with the selecting device, at least one point in the set, and opening, on the computer, to the part of the electronic document associated with the point selected by the selecting device.

Abstract: A device including a wooden, metal or plastic substrate having at least a back surface, a front surface, and a depth portion located between the back surface and the front surface. Further, the device includes an indentation having a length and a width on the front surface, wherein the length is longer than the width and the length is oriented perpendicular to the depth portion. Further still, the device includes an attachment apparatus connected to the back surface, wherein the attachment apparatus is for attaching the device to an object, such as a golf bag. Yet further, the device includes an adjustable strap connected to the device and traversing at least the width. Thereby, the device allows one or more items, such as a pen, pencil, cigar or cigarette, to be placed in the indentation and securely held in place by the adjustable strap, such as an elastomeric band.

Abstract: Systems, methods and media for awarding credits based on provided usage information are disclosed. More particularly, hardware and/or software for collecting and disseminating usage information related to electronic documents and for awarding usage credits to users in exchange for providing usage information are disclosed. Embodiments include receiving an indication of the usage of an electronic document by a user and aggregating the received usage indication for the document with usage indications relating to other users. Embodiments may also include creating document utilization information for the electronic document based on the aggregated usage indications and awarding usage credit to the user based on the user's providing statistics on the usage of the electronic document. Further embodiments may include transmitting an indication of the awarded usage credit to the user and receiving a request to use the usage credits.

Abstract: The decision within a packet processing device to transmit a newly arriving packet into a queue to await further processing or to discard the same packet is made by a flow control method and system. The flow control is updated with a constant period determined by storage and flow rate limits. The update includes comparing current queue occupancy to a threshold. The outcome of the update is adjustment up or down of the transmit probability value. The value is stored for the subsequent period of flow control and packets arriving during that period are subject to a transmit or discard decision that uses that value.

Abstract: Improved methods, systems, and apparatuses are disclosed for testing LGA devices. One example embodiment include vertical routing of test nest assembly cooling lines in order to minimize the test nest footprint and increase available test sites on a single test card. Another example embodiment includes isolating and adjusting external loads and moments into the heatsink/cold plate, wherein these loads and moments involve controlling the centroid to restore more ideal thermal performance of the heatsink/chip interface. Still another example embodiment includes a nest architecture facilitating easy and low-cost replacement of LGA sockets. Finally, another example embodiment includes efficient condensation control of test nest assembly parts by using dry-air exhaust.