Abstract: Embodiments of the invention provide a flexible probe head that improves contact force and uniform mechanical contact pressure between the probe feature and an engaged bond pad. Flexible probe head is formed from a plurality of conductive wires embedded in a high frequency elastomer material. During wafer sort, the flexible probe head is in contact communication with die under test. The flexible probe head assumes the natural co-planarity of the surface of the die under test and sort interface unit.

Abstract: Method for determining entropy of a pixel of a real time streaming digital video image signal, particularly applicable for identifying the origin of, and processing, in real time, pixels of interlaced, non-interlaced, or de-interlaced, streaming digital video image signals, and for correcting errors produced during editing of streaming digital video image signals. Based upon the fundamental aspect of determining the degree or extent of randomness or disorder, or entropy, and determining the fluctuation thereof, of each pixel relative to inter-local neighborhoods and intra-local neighborhoods of selected pixels originating from the streaming digital video image input signal. Automatically detects and identifies original mode of the video input signal (film movie, video camera, or graphics). Independent of type of mode conversion used for generating the original video input signal, and not based upon an ‘a priori’ type of pattern recognition method.

Abstract: In one embodiment, a method of performing video image decoding includes the following. A compressed video image is downsampled in the frequency domain. The downsampled video image is inverse transformed. Motion compensation for the downsampled image is performed in the spatial domain.

Abstract: Embodiments of the invention provide an automatic address generator that generates an address sequence directly using counters that count between predefined start and stop values in accordance with a predefined modes of indexing. The counters support slipping when counting to support convolutional filters in one-dimension (1D) and two-dimension (2D). For 2D indexing, a first counter indexes in the X direction and a second counter indexes in the Y direction in memory. The values from the first and second counter are combined with an offset value to form an address directly to memory.

Abstract: An ACPI (Non-Volatile Sleeping) NVS memory region is allocated and defined so that a system BIOS can allocate a placeholder for the different parameters that are passed from the ACPI ASL code to the system management mode (SMM) handler for execution of real mode calls. The different parameters will be updated by runtime ACPI ASL code depending on what needs to be passed to the SMM handler. The SMM handler invokes appropriate calls based on retrieving of different parameters in the ACPI NVS memory region that have been passed from the ACPI ASL code.

Abstract: Briefly, in accordance with one embodiment of the invention, a digital camera includes: a digital imaging array including a plurality of pixels, and image processing circuitry to process the digital pixel output signals produced by the imaging array. The imaging processing circuitry is adapted to process saturated digital pixel output signals differently from non-saturated digital pixel output signals. In accordance with another embodiment of the invention, at least one integrated circuit includes image processing circuitry. The processing circuitry is adapted to process digital pixel output signals produced by a digital imaging array. The image processing circuitry is further adapted to process saturated digital pixel output signals differently from non-saturated digital pixel output signals.

Abstract: A method of converting from a sub-sampled color image in a first color space format to a full color image in a second color space format includes the following. A sub-sampled color image in a first color space format is transformed to a second color space format. At least one color plane of the transformed image is upscaled, the one color plane corresponding to one of the color space dimensions of the second color space format, to provide the full color image in the second color space format. Of course, many other embodiments other than the preceding embodiment are also within the scope of the present invention.

Abstract: Embodiments of the present invention provide an algorithm for scheduling read and write transactions to memory out of order to improve command and data bus utilization and gain performance over a range of workloads. In particular, memory transactions are sorted into queues so that they do not have page conflict with each other and are scheduled from these queues out of order in accordance with read and write scheduling algorithms to optimize latency.

Abstract: Embodiments of the present invention provide for enumerating codecs on a link. A controller asserts a synchronization signal, and drives one or more control lines associated with selected codecs to a first state. The enumeration period is defined by a predefined number of clock periods after de-assertion of the synchronization signal. During the enumeration period, the controller drives the control lines of codecs that are supported to a second state. If the control line for a codec is not pulled to the second state during the enumeration period, that codec will act disabled, ignoring all inputs, and will not participate in any link activity, until the next reset, where it will again look for an assertion of its control line.

Abstract: Embodiments of the present invention provide a method and apparatus to allow an I/O controller to alert an external controller using an enhanced SMBus implementation that enables bi-directional capability on SMBALERT#. I/O controller includes an auxiliary control register and alert output enable (AOEN) register. When host sets AOE bit in auxiliary control register, SMBALERT# signal is configured as an output signal with bi-directional functionality. External controller uses an interface command to write to AOEN register and determine events/conditions it wants to be alerted on. SMBALERT# is activated in response to a detected event/condition. In response to SMBALERT#, external controller determines the alert generation condition using byte read commands on the system management bus, and clears SMBALERT#.

Abstract: When encoding and decoding bit planes, a decision is made in the clean up pass if zero coding or run length coding should be performed. Embodiments of the invention provide a zero coding or run length coding decision instruction. The instruction will determine whether significance state variables associated with selected coefficients bits and their immediate neighbors are zero. If all the significance states are determined to be zero, then run length coding is performed. Else, zero coding is performed.

Abstract: Embodiments of the present invention provide a method and apparatus for detecting an interruption in memory initialization. A status bit for indicating whether memory initialization was interrupted or not is stored in a register. A basic input/output system (BIOS) sets the status bit prior to initialization and clears the status bit after initialization. The status bit cannot be reset by a standard platform reset. In operation, as the system is reset or turned on and prior to initialization, the BIOS checks the status bit to detect possible improper memory initialization. When the status bit is set, the BIOS concludes that a memory initialization had not completed and thus might be incorrect. The BIOS then causes power to be cycled to memory and any other steps needed are taken to return the memory to a functional state.

Abstract: Embodiments of the present invention provide an edge adaptive spatial temporal deinterlacing filter that evaluates multiple edge angles and groups them into left-edge and right-edge groups for reconstructing desired pixel values. A leading edge is selected from each group, forming the final three edges (left, right and vertical) to be determined. Spatial temporal filtering is applied along the edge directions.

Abstract: Embodiments of the present invention detect a device's ability to run at a particular frequency on a PCI bus operating in a non-inhibit bus mode. In one embodiment, expansion slots are powered on, connected to the PCI bus and reset. The expansion slots are then disconnected from the PCI bus while power is applied. A frequency detection algorithm, which is operable regardless of the inhibit bus connect setting or capability, is executed. The expansion slots are then reconnected to the PCI bus.

Abstract: Embodiments of the present invention provide a memory arbiter for directing chipset and graphics traffic to system memory. Page consistency and priorities are used to optimize memory bandwidth utilization and guarantee latency to isochronous display requests. The arbiter also contains a mechanism to prevent CPU requests from starving lower priority requests. The memory arbiter thus provides a simple, easy to validate architecture that prevents the CPU from unfairly starving low priority agent and takes advantage of grace periods and memory page detection to optimize arbitration switches, thus increasing memory bandwidth utilization.

Abstract: A 3D rendering texture caching scheme that minimizes external bandwidth requirements for texture and increases the rate at which textured pixels are available. The texture caching scheme efficiently pre-fetches data at the main memory access granularity and stores it in cache memory. The data in the main memory and texture cache memory is organized in a manner to achieve large reuse of texels with a minimum of cache memory to minimize cache misses. The texture main memory stores a two dimensional array of texels, each texel having an address and one of N identifiers. The texture cache memory has addresses partitioned into N banks, each bank containing texels transferred from the main memory that have the corresponding identifier. A cache controller determines which texels need to be transferred from the texture main memory to the texture cache memory and which texels are currently in the cache using a least most recently used algorithm.

Abstract: Briefly, in accordance with one embodiment, a technique for coding the movement of a head or face from a sequence of images is disclosed. A variety of potential alternative embodiments are discussed.

Abstract: Briefly, in accordance with one embodiment on the invention, a method of compressing a data set includes the following. In multiple passes, each data signal in the data set is categorized into a category of a predetermined set, and, for selected categories of the predetermined set, the data signals for that category are coded using a codebook for that category. Briefly, in accordance with another embodiment of the invention, a method of decompressing a compressed data set includes the following. For compressed data signals in the data set in one category of a predetermined set of categories, a signal associated with the particular category is employed for the compressed data signal, and, for selected categories of the predetermined set, the compressed data signals for that category are decoded using a codebook for that category.

Abstract: In particular, the present invention relates to a method and system for improving the efficiency of computational processes and specifically multiply and accumulate (“MAC”) processes such as the DCT (“Discrete Cosine Transform”) and/or IDCT (“Inverse Discrete Cosine Transform”) using a performance optimized method and associated hardware apparatus.

Abstract: Embodiments of the present invention provide for an ACPI Non-Volatile Sleeping (NVS) memory region that is allocated and defined so that a system BIOS can save CMOS based memory content at the ACPI NVS memory region during power on system test (POST). The ACPI NVS memory region and it's associated content, is accessible to both OS and non-OS software during runtime execution.