Abstract: Embodiments of the present invention provide a method and apparatus for optimally mapping a tiled memory surface to two memory channels, operating in an interleaved fashion, maximizing the memory efficiency of the two channels, while maintaining the desired access granularity. In particular, an incoming request address is used to generate memory addresses for memory channels based on tile and request parameters. The memory controller stores the set of tiled data in the memory in a format such that selected sets of tiled data are stored in alternating channels of memory, such that data blocks are accessible at the same time, as opposed to sequentially. Thus if the memory controller received a block of data from a source, such as a graphics engine, the memory controller would store portions of the block of data within a single tile in the memory, partitioned such that it is retrievable via alternate channels of memory at the same time.

Abstract: The present invention optimizes graphics performance during zone rendering by providing an automatic management of bin memory between the binning and rendering phases. Embodiments of the present invention provide a mechanism by which the binner and renderer automatically share a pool of physical memory pages in order to build bin buffers and recycle them after they have been used in rendering. This is performed in such a fashion that multiple binned scenes can be queued up concurrently, with no requirement for software intervention except under exceptional conditions. The need for software management of zone rendering bin buffer memory is thus eliminated. Multiple scenes for binning and rendering can also be queued without software intervention.

Abstract: Embodiments of a method of performing Huffman decoding are disclosed. In one such embodiment, a data structure is employed, although, of course, the invention is not limited in scope to the particular embodiments disclosed.

Abstract: Briefly, in accordance with one embodiment of the invention, a method of inverse quantizing quantized signal samples of an image during image decompression includes the following. A process to transform the signal samples from a first domain to a second domain is applied. During the transform process, signal samples are filter, by first applying scaled filter coefficients to signal samples along the image in a first direction and then applying scaled filter coefficients to signal samples along the image in a second direction, so that at the completion of the transform process of the image, at least a selected portion of the transformed signal samples are inverse quantized. Many other embodiments in accordance with the invention are also described.

Abstract: Embodiments of the invention provide for a delay locked loop architecture including a coarse-fine type arrangement using one loop for non-continuous strobe that can be also be configured for continuous clocks as well. In particular, a reference loop establishes precise coarse unit delay. A slave delay line duplicates unit delay. A phase interpolator interpolates between unit delay to produce fine delay.

Abstract: Embodiments of a three-dimensional wavelet transform are described. An inverse three-dimensional discrete wavelet transformation (IDWT) is applied to a plurality of transformed video image sub-blocks. The sub-blocks of transformed video images are inverse transformed by applying a bit-based conditional decoding to the embedded zero tree encoded DWT coefficients of the block to obtain a DWT coefficient matrix, up-sampling respective sub-blocks of the DWT coefficient matrix by row, column and frame, filtering and combining one or more respective pairs of up-sampled sub-blocks to produce an up-sampled sub-block corresponding to each respective pair, reapplying the filtering and combining step to any produced up-sampled sub-block pairs until one up-sampled sub-block remains and multiplying the one remaining up-sampled sub-block by eight to produce a block at the next higher resolution.

Abstract: A depth write disable apparatus and method for controlling evictions, such as depth values, from a depth cache to a corresponding depth buffer in a zone rendering system. When the depth write disable circuitry is enabled, evictions from the depth cache (as which typically occur during the rendering of the next zone) to the depth buffer are prevented. In particular, once the depth buffer is initialized (i.e. cleared) to a constant value at the beginning of a scene, the depth buffer does not need to be read. The depth cache handles intermediate depth reads and writes within each zone. Since the memory resident depth buffer is not required after a scene is rendered, it never needs to be written. The final depth values for a zone can thus be discarded (i.e., rather than written to the depth buffer) after each zone is rendering.

Abstract: Embodiments of the present invention provide a split vertex buffer where the data for each vertex is split between parallel vertex buffers. The first buffer contains vertex X and Y data, while the second parallel buffer contains the remainder of the vertex data. Given the split vertex buffers, the hardware binning-engine is now permitted to read and cache only vertex screen X and Y data. Especially given a typically high level of temporal coherency between indexed vertex references, the reading and caching of large parcels of vertex screen-space X and Y leads to lower and highly efficient utilization of memory bandwidth for hardware binning input. Embodiments of the present invention thus reduce the hardware binning memory bandwidth requirements and improve memory utilization.

Abstract: Embodiments of the invention provide an anisotropic filtering configuration where a ratio value is computed as the ratio of the major axis to the minor axis of a pixel projection on a texture map. The number of subpixels generated and sampled is based upon the value of the ratio. For four-way anisotropic filtering, subpixels are generated that move as the computed ratio between the major and minor axis increases. Subpixels may be placed anywhere from 0.5 to 1.5 texel distance from the pixel center depending on the computed ratio. The contribution of the subpixels is equally weighted.

Abstract: In some embodiments, the invention includes a method to bit scramble a digital video signal. The method includes receiving blocks of the digital video signal and scrambling the blocks of the digital video signal responsive to a remote computer number. The remote computer number may be a processor number of a remote computer that may descramble the bit scrambled video signal. In other embodiments, the invention includes a method to descramble a bit scrambled video signal in a computer. The method includes receiving blocks of the bit scrambled video signal and descrambling the blocks of the bit scrambled video signal responsive to a remote computer number of the computer in which the descrambling is occurring. Additional embodiments are described and claimed.

Abstract: A texture data reading apparatus includes a cache memory including a plurality of read ports and a plurality of regions to store pixel texture data. An address comparator includes a plurality of input ports to receive incoming pixels, wherein the address comparator compares the memory addresses associated with the incoming pixels to determine which regions of cache memory are accessed. A cache lookup device accesses new texture data from the cache memory for the incoming pixels in the same clock cycle in response to the number of memory regions accessed being less than or equal to the number of cache memory read ports.

Abstract: Embodiments of the present invention provide for adaptively tuning the memory idle timer value in real time. Selected memory idle clock cycles are sampled to dynamically determine an optimized memory idle timer value. To optimize latency during sampling, the number of page hits (NPH) and number of page misses (NPM) are multiplied by weighted values WPH and WPM, respectively, such that the weighted function (WPH*NPH)?(WPM*NPM) is maximized. The weight associated with a page miss (WPM) is greater than the weight associated with a page hit (WPH), resulting in a bigger penalty for a page miss than a page hit. The selected setting is continuously optimized.

Abstract: Briefly, in accordance with one embodiment of the invention, a video processing system includes: a video coder. The video coder includes the capability to generate an edge detection map along a predetermined direction for an uncoded frame that is to be coded. Briefly, in accordance with another embodiment of the invention, an article includes: a storage medium having stored thereon instructions capable of being executed by a system that when executed result in: producing an edge detection map along a predetermined direction from the video frame prior to coding; and coding the edge detection map and the video frame. Briefly, in accordance with one more embodiment of the invention, a method of processing a video frame includes: producing an edge detection map along a predetermined direction from the video frame prior to coding; and coding the edge detection map and the video frame.

Abstract: Embodiments of the present invention provide for implementation of data transfers in an efficient manner. The 48-bit LBA mechanism requires two sets of I/O writes to IDE registers on primary channel or secondary channel. The two sets of I/O writes to the primary or secondary channel registers are performed by setting a status register to a first or second state appropriately depending on the data. Embodiments of the present invention provide a single set of writes to I/O registers when the size of the data transfer is equal to or below a threshold value.

Abstract: Embodiments of the present invention efficiently support rendering of high resolution images under zone rendering. In particular, a bin array rectangle and binner clipping rectangle for determining primitive-zone intersections. Both of these rectangles are defined by graphics device state variables containing the screen-space location of the rectangle corners. In particular, the binner clipping rectangle is used to define the visible region in screen coordinates. Objects completely outside the binner clipping rectangle in one or more directions will be discarded. Objects that cannot be trivially rejected are subjected to bin determination. The bin array rectangle handles color buffer resolutions larger than could otherwise be accommodated by the optimally-renderer image limits.

Abstract: A computer graphics system is provided that includes a memory to store image data, a bin pointer list to store information regarding a plurality of image subscenes, and a pointer cache system to maintain data regarding the plurality of image subscenes. The pointer cache system may include a tag array section, a data array section and a decoupling section.

Abstract: Embodiments of a method and apparatus for coding and decoding wavelet transformed coefficients is described.

Abstract: Briefly, in accordance with one embodiment of the invention, a method of producing quantization error signal samples for a layer of a multi-layer coder applied to successive video frames includes: processing in the transform domain quantization error signal samples produced by the immediately preceding layer. In this embodiment, processing includes using reference quantization error signal samples if the quantization error for the quantization error signal samples exceeds a predetermined criterion or threshold.

Abstract: Embodiments of the present invention provide a memory arbiter for directing chipset and graphics traffic to system memory. Page consistency and priorities are used to optimize memory bandwidth utilization and guarantee latency to isochronous display requests. The arbiter also contains a mechanism to prevent CPU requests from starving lower priority requests. The memory arbiter thus provides a simple, easy to validate architecture that prevents the CPU from unfairly starving low priority agent and takes advantage of grace periods and memory page detection to optimize arbitration switches, thus increasing memory bandwidth utilization.

Abstract: Embodiments of the present invention are disclosed in which one dimensional image compression, such as for bi-level images, is implemented. An integrated circuit includes digital logic circuitry and digital memories. The digital logic circuitry and digital memories are coupled so as to implement one dimensional compression of a bit stream to be applied to the digital logic circuitry and digital memories without performing arithmetic operations. One of the digital read only memories stores, for a plurality of run lengths, a memory address for a make up code and a memory address for a termination code for the respective run lengths.