Patents Represented by Attorney Sharon Wong
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Patent number: 6771834Abstract: Briefly, in accordance with one embodiment of the invention, a method of segmenting an initial digital image includes the following. The initial digital image is processed to produce a first digital image with defined edges corresponding to the initial digital image and to produce a second digital image with at least two dominant contiguous regions corresponding to the initial digital image. Distinct non-overlapping regions of the first digital image formed by the defined edges are identified. The distinct non-overlapping regions of the first digital are combined based, at least in part, on a correspondence with the at least two dominant contiguous regions in the second digital image. Based, at least in part, on the remaining regions after combining the distinct non-overlapping regions of the first digital image, the initial digital image is segmented.Type: GrantFiled: July 2, 1999Date of Patent: August 3, 2004Assignee: Intel CorporationInventors: Fernando C. M. Martins, Rajeeb Hazra
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Patent number: 6766286Abstract: Embodiments of a pyramid filter are described.Type: GrantFiled: March 28, 2001Date of Patent: July 20, 2004Assignee: Intel CorporationInventor: Tinku Acharya
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Patent number: 6762765Abstract: Embodiments of the present invention provide a split vertex buffer where the data for each vertex is split between parallel vertex buffers. The first buffer contains vertex X and Y data, while the second parallel buffer contains the remainder of the vertex data. Given the split vertex buffers, the hardware binning-engine is now permitted to read and cache only vertex screen X and Y data. Especially given a typically high level of temporal coherency between indexed vertex references, the reading and caching of large parcels of vertex screen-space X and Y leads to lower and highly efficient utilization of memory bandwidth for hardware binning input. Embodiments of the present invention thus reduce the hardware binning memory bandwidth requirements and improve memory utilization.Type: GrantFiled: December 31, 2001Date of Patent: July 13, 2004Assignee: Intel CorporationInventors: Peter L. Doyle, Thomas A. Piazza
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Patent number: 6747658Abstract: The present invention optimizes graphics performance during zone rendering by providing an automatic management of bin memory between the binning and rendering phases. Embodiments of the present invention provide a mechanism by which the binner and renderer automatically share a pool of physical memory pages in order to build bin buffers and recycle them after they have been used in rendering. This is performed in such a fashion that multiple binned scenes can be queued up concurrently, with no requirement for software intervention except under exceptional conditions. The need for software management of zone rendering bin buffer memory is thus eliminated. Multiple scenes for binning and rendering can also be queued without software intervention.Type: GrantFiled: December 31, 2001Date of Patent: June 8, 2004Assignee: Intel CorporationInventors: Peter L. Doyle, Aditya Sreenivas
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Patent number: 6747653Abstract: Similar, contiguous primitives are stored as a single primitive in zone rendering bins. A primitive packet used in the bin is allowed to vary in length and the currently open type of primitive is recorded on a per-bin basis. A special code is used to specify a variable number of subsequent indices. With this mechanism, the hardware is able to start outputting and replicating primitive commands into bin lists on the fly without requiring the buffering of the entire primitive. Given the variable nature of the primitive instruction, multiple similar/sequential primitives can be concatenated using a single primitive command header.Type: GrantFiled: December 31, 2001Date of Patent: June 8, 2004Assignee: Intel CorporationInventor: Peter L. Doyle
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Patent number: 6748118Abstract: Briefly, in accordance with one embodiment of the invention, a method of quantizing signal samples of an image during image compression includes the following. A process to transform the signal samples from a first domain to a second domain is applied. During the transform process, signal samples are filter, by first applying scaled filter coefficients to signal samples along the image in a first direction and then applying scaled filter coefficients to signal samples along the image in a second direction, so that at the completion of the transform process of the image, selected regions of the transformed signal samples are quantized by a common value. Many other embodiments in accordance with the invention are also described.Type: GrantFiled: February 18, 2000Date of Patent: June 8, 2004Assignee: Intel CorporationInventors: Tinku Acharya, Ping-Sing Tsai
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Patent number: 6738520Abstract: Several embodiments in accordance with the invention are disclosed. An embodiment for compressing a gray scale image is described and an embodiment for decompressing the codebook produced by compressing the gray scale image is described. Of course, the invention is not limited to only gray scale images, however.Type: GrantFiled: June 19, 2000Date of Patent: May 18, 2004Assignee: Intel CorporationInventors: Tinku Acharya, Bhargab Bikram Bhattacharya, Malay Kumar Kundu, Suman Kumar Mitra, Chivukula A. Murthy
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Patent number: 6725247Abstract: An integrated circuit has a two-dimensional pyramid filter architecture of an order 2N−1, where N is a positive integer greater than five. The two dimensional pyramid filter, in operation, capable of producing, on respective clock cycles, pyramid filtered output signals corresponding to output signals produced by fourteen one-dimensional pyramid filters of order 2N−1, and pyramid filtered output signals corresponding to output signals produced either by four two-dimensional pyramid filters or one two-dimensional pyramid filter of order [2(N−1)−1] using signal sample matrices of order [2(N−1)−1]. The respective output signals in said two-dimensional pyramid filter architecture are summed on respective clock cycles of said two dimensional pyramid filter architecture.Type: GrantFiled: April 30, 2001Date of Patent: April 20, 2004Assignee: Intel CorporationInventor: Tinku Acharya
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Patent number: 6697534Abstract: Briefly, in accordance with one embodiment of the invention, a method of sharpening an image includes the following. A crispening parameter is adaptively computed for a local region of a captured image based, at least in part, on a measure of the local contrast and the local brightness. A kernel is applied to the local region of the captured image using the adaptively computed crispening parameter.Type: GrantFiled: June 9, 1999Date of Patent: February 24, 2004Assignee: Intel CorporationInventors: Yap-Peng Tan, Ping-Sing Tsai, Tinku Acharya
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Patent number: 6694401Abstract: Embodiments of the present invention provide for executing real-mode interrupts from within an extended SMRAM handler. If there is a need to make a real-mode call from the extended SMRAM handler, control is transferred to a compatible SMRAM region and appropriate calls to the real-mode calls are executed from within the compatible SMRAM region. The call from the extended SMRAM handler code to the compatible SMRAM code switches the processor from protected mode to real-mode. After the real-mode call is complete, control is returned to the compatible SMRAM handler. The processor is placed back into protected mode and control transferred back to the extended SMRAM handler code.Type: GrantFiled: December 28, 2001Date of Patent: February 17, 2004Assignee: Intel CorporationInventors: Rajeev K. Nalawadi, Dong H. Thai
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Patent number: 6671419Abstract: Briefly, in accordance with one embodiment of the invention, a method of reducing shadows and/or noise in a digital image includes the following. A noise floor for the digital image is estimated. A threshold level for a difference image of the digital image and a background image is determined based, at least in part, on the noise floor estimate. The digital image is modified based, at least in part, on the determined threshold level and the difference image.Type: GrantFiled: July 2, 1999Date of Patent: December 30, 2003Assignee: Intel CorporationInventor: Fernando C. M. Martins
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Patent number: 6662200Abstract: Embodiments of a multiplierless pyramid filter are described.Type: GrantFiled: January 3, 2001Date of Patent: December 9, 2003Assignee: Intel CorporationInventor: Tinku Acharya
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Patent number: 6640017Abstract: Briefly, in accordance with one embodiment of the invention, a method of sharpening an image includes the following. A crispening parameter is adaptively computed for a captured image based, at least in part, on a measure of the edges and brightness of the captured image. A kernel is applied to the captured image using the adaptively computed crispening parameter.Type: GrantFiled: May 26, 1999Date of Patent: October 28, 2003Assignee: Intel CorporationInventors: Ping-Sing Tsai, Yap-Peng Tan, Tinku Acharya
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Patent number: 6625308Abstract: Embodiments of a fuzzy distinction based thresholding technique for image segmentation are disclosed. In one embodiment, at least one signal value level of the image is determined along which to divide a fuzzy histogram, the histogram being based, at least in part, on the image. The signal value represents a value which produces a divided fuzzy histogram with an extreme value of one of distinctiveness and fuzziness based on a measure of multidimensional distance between measurement distributions and their respective complements. The image is then segmented using the at least one signal value.Type: GrantFiled: September 10, 1999Date of Patent: September 23, 2003Assignee: Intel CorporationInventors: Tinku Acharya, Ajay K. Ray, A. K. V. Subba Rao
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Patent number: 6597373Abstract: A display controller that includes a controller adapted to receive images selectable in real-time to any of a two or more of differing scanning resolutions, adapted to receive information regarding a fixed scanning resolution of a display device, and adapted to generate image borders taking into consideration the information of the fixed scanning resolution and a currently selected one of the two or more differing scanning resolutions, in order to control placement of the images on the display device.Type: GrantFiled: January 7, 2000Date of Patent: July 22, 2003Assignee: Intel CorporationInventors: Ashutosh Singla, Richard W. Jensen, Kim A. Meinerth, Paul A. Jolly