Abstract: A handheld computer having a housing with a midframe construction is described. The housing includes a front shell and a back shell coupled to a midframe. The handheld computer also includes two accessory slots for a stylus or other devices on the left and right sides of the housing. The handheld computer also includes an infrared port which is an integral portion of the housing.

Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated with a phase offset relative to a first clock signal in accordance with a first programmed value, and a second timing signal is generated with a phase offset relative to the first clock signal in accordance with a second programmed value. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

Abstract: A content addressable memory (CAM) device having CAM cells arranged in rows and columns. A plurality of first data line pairs extend along respective columns of the CAM cells. A plurality of second data line pairs extend along respective columns of the CAM array adjacent the first data line pairs, each second data line pair having a first and second constituent data lines that cross one another at a point along their lengths.

Abstract: A wide-range multi-phase clock generator having a first clock generating circuit, a frequency divider circuit, and a plurality of multiplexers. The first clock generating circuit generates a plurality of first clock signals, each having a first frequency and a respective one of a plurality of different phase angles. The frequency divider circuit receives the plurality of first clock signals from the first clock generating circuit, and generates a plurality of second clock signals, each having a second frequency and a respective one of the plurality of different phase angles. The multiplexers each have a first input coupled to receive a respective one of the first clock signals and a second input coupled to receive a respective one of the second clock signals having substantially the same phase angle as the one of the first clock signals.

Abstract: A sense amplifier circuit with faster sensing speed and improved insensitivities to fabrication process variations (i.e., eliminated functional failures) is provided herein. According to one embodiment, the sense amplifier circuit associated with a row of memory cells within a memory device may include a charging portion, which is coupled for receiving a reference voltage that is supplied to at least one additional sense amplifier circuit within the memory device. The reference voltage is provided by a current reference generator, which is coupled to the sense amplifier circuit(s) for detecting: (i) a maximum amount of current that can pass through one compare stack within the memory cell array, or (ii) a difference between the maximum amount of current and the current contribution of an n-channel current source within the sense amplifier circuit. A memory device and method of operating one embodiment of the improved sense amplifier circuit are also provided herein.

Abstract: Systems and methods for generating write data signals having variable delays for use in write operations to memory components are provided. These memory systems and methods include receiving a write data signal and a corresponding data valid or timing signal (also referred to as a write data valid signal or write data timing signal) and in turn generating multiple delayed versions of the write data signals and delayed valid signals. The memory system selects one of these delayed write data signals and delayed data valid signals for use in writing data to the memory components.

Abstract: Embodiments of this invention provide for a portable computer that determines whether an accessory device is actively connected to it. In one embodiment, the portable computer may include a signal line accessible through an output of the portable computing device. The signal line may be connected to a communication device such as a communication cradle. The portable computer may detect a signal on the signal line to determine whether the communication device is actively connected to the portable computer. If the communication device is actively connected, the portable computer suspends implementation of a time-out feature that would otherwise reduce power consumption of the portable computer.

Abstract: A keypad is provided for a computing device. The keypad includes one or more lighting devices or mechanisms for illuminating a plurality of keys structures. In an embodiment, the plurality of key structures are formed from a milky material.

Abstract: A content addressable memory (CAM) device with selective error logging. The CAM device includes a CAM array and an error detection circuit coupled to receive a data value from a selected storage location within the CAM array, the error detection circuit being adapted to generate an error indication according to whether the data value includes an error. An error storage circuit is coupled to receive the error indication from the error detection circuit and is adapted to store an error address that corresponds to the selected storage location if the error indication indicates that the data value includes an error and if the error address is not already stored within the error storage circuit.

Abstract: A self-calibrating analog-to-digital converter (ADC). The ADC includes multiple component ADCs to generate respective digital representations of an input signal in response to respective timing signals that are offset in phase from one another, each component ADC having a gain setting that controls a magnitude of the digital representations. The ADC further includes correction circuitry to generate a plurality of fast-Fourier transforms (FFTs) that correspond to the digital representations of the input signal and to adjust the gain settings of the component ADCs and/or phase angles of the timing signals based on gain and phase errors indicated by the FFTs.

Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. During a third mode of operation, a first plurality of storage cells in a first row of storage cells in a first memory bank is accessible in response to a first column address.

Abstract: A method and system to provide media to a terminal coupled to a network, the terminal comprising a media playback component. The method and system provides for programmatically directing the terminal to access a first network site in the plurality of network sites, and causing the media playback component on the terminal to automatically load a first media web resource located at the first network site to playback a first media. The method and system also includes programmatically directing the terminal to access a second network site in the plurality of network sites, and causing the media playback component on the terminal to automatically load a second media web resource located at the second network site to playback a second media.

Abstract: A keypad is provided for a computing device. The keypad includes one or more lighting devices or mechanisms for illuminating a plurality of keys structures. In an embodiment, the plurality of key structures are formed from a milky material.

Abstract: A digital signal processor having priority logic coupled to an array of storage elements, the priority logic to provide to a priority signal lines an indication of a location of a particular number in the array of storage elements. The priority logic includes compare circuits where each compare circuit is coupled to one of the storage elements in the array of storage elements. Each compare circuit has a first input coupled to a storage element, a second input coupled to a match line, and an input/output line coupled to one of the priority signal lines. The priority logic also includes a delay circuit coupled to each of the compare circuits.

Abstract: A key structure assembly is provided for a mobile computing device. The key structure assembly includes a keycap having at least a first segment and a second segment. A first actuation member extends inward into the housing from the first segment of the keycap, and a second actuation member extends inward from the second segment of the key cap. A substrate including a plurality of electrical connects, including a first electrical contact aligned underneath the first actuation member, and a second electrical contact aligned underneath the second actuation member. The keycap is moveable inward to direct either the first actuation member into contact with the first electrical contact, or the second actuation member into contact with the second electrical contact. One or more sections of material are positioned above the first electrical contact and the second electrical contact.

Abstract: An electronic device is provided that includes a user-interface feature, a detection mechanism and one or more internal components. The user-interface feature is configurable to have a selected orientation about one or more axes. The detection mechanism can detect orientation information about the electronic device. The one or more components may select the orientation of the user-interface feature based on the detected orientation information.

Abstract: A content addressable memory (CAM) device including a CAM array, encoding circuit, address circuit and error checking circuit. The encoding circuit generates an address value that corresponds to one of a plurality of match lines included within the CAM array. The address circuit receives the address value from the encoding circuit and enables a data word to be output from a CAM array storage location indicated by the address value. The error checking circuit receives the data word output from the storage location and determines whether the data word contains an error.

Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Abstract: A CAM and method for operating a CAM are presented. Copies of a CAM database are duplicated and placed in a first set of CAM locations and a second set of CAM locations. An error detector is used to determine false matches in the case of soft errors within the entries producing those false matches. While the entries producing a match should have the same index location, errors might cause those match lines to have an offset. If so, the present CAM, through use of duplicative sets of CAM locations, will detect the offset and thereafter the values in each index location that produces a match, along with the corresponding parity or error detection encoding bit(s). If the parity or error detection encoding bit(s) indicate an error in a particular entry, then that error is located and the corresponding entry at the same index within the other, duplicative set of CAM locations is copied into the that erroneous entry.