Abstract: A capacitor of a semiconductor device and a method for manufacturing the same includes a lower metal layer on and/or over a semiconductor substrate; an insulating layer formed on and/or over the lower metal layer with step difference; and an upper electrode on and/or over the insulating layer pattern, wherein a top corner of the upper electrode is rounded so that a curvature pattern is formed on the top corner of the upper electrode.

Abstract: According to the present application, a method of manufacturing a piezoelectric transistor may include forming a cavity over a substrate, such as a semiconductor substrate. The method may include depositing and patterning metal material over a portion of a cavity, and may include depositing an oxide film over a cavity and/or patterned metal material. Piezoelectric material may be deposited over an oxide film and patterned to avoid connection with metal material. The method may include depositing a second oxide film over a substrate including piezoelectric material. Metal wiring may be formed and may apply voltage to piezoelectric material that may be in contact with a semiconductor substrate.

Abstract: An image sensor of a semiconductor and a method for fabricating the same includes a photodiode; an interlayer dielectric layer formed over the photodiode; a wave guide including an ion implantation layer formed in the interlayer dielectric; a color filter formed over the interlayer dielectric layer; and a micro lens formed over the color filter.

Abstract: A current sensing circuit includes a power transistor, a sensing transistor configured to copy a current flowing through the power transistor at a predetermined ratio, a current sensing resistor configured to detect a voltage from the current copied by the sensing transistor, an input resistor configured to convert an input voltage to a current, a cross self-biasing cascade block configured to adjust currents at both ends of the input resistor, and a common gate transistor and a reference resistor configured to convert a current output of the input resistor to a final sense voltage.

Abstract: A method of opening a pad in a semiconductor device. A protective film on a pad may be etched with a pad opening pattern as a mask. Dielectric heating may be performed on the pad opened by etching the protective film. Organic material containing C and F groups on the pad may be removed by heating with molecular vibration and/or microwaves, which may substantially prevent and/or minimize corrosion.

Abstract: A method of forming an isolation layer in a semiconductor device is disclosed, by which breakdown voltage and PN junction leakage characteristics of the isolation layer are enhanced. Embodiments include depositing a pad nitride layer over a semiconductor substrate, reducing the thickness of the pad nitride layer by etching a portion of the pad nitride layer, forming a tetraethyl orthosilicate (TEOS) oxide layer over the remaining pad nitride layer, forming a trench by selectively removing the tetraethyl orthosilicate oxide layer and the pad nitride layer over an isolation area of the semiconductor substrate, depositing an high density plasma oxide layer over the substrate to fill the trench, and forming an isolation layer by planarizing the high density plasma oxide layer and the tetraethyl orthosilicate oxide layer.

Abstract: Provided is a liquid crystal display (LCD) without a color filter, the LCD including: a liquid crystal panel comprising front and rear glass substrates and a plurality of red, green, and blue liquid crystal subpixels disposed between the front and rear glass substrates corresponding to red, green, and blue lights, respectively; a backlight unit disposed in rear of the liquid crystal panel and comprising a plurality of three-color light supply units supplying the red, green, and blue lights, respectively, and separated from one another so that the plurality of three-color light supply units are compartmentalized; and a lenticular lens array disposed between the liquid crystal panel and the backlight unit, inducing the red, green, and blue lights irradiated by the three-color light supply units into the red, green, and blue liquid crystal subpixels included in the liquid crystal panel and comprising a plurality of lenticular lens groups comprising a plurality of lenticular lenses, wherein the plurality of lenti

Abstract: Provided is a flexible wire to be inserted in a pipe and rotated in a high speed to remove scales in the pipe by striking the scales. The flexible wire includes a main wire line which is formed by alternately winding a central wire line with clockwise and counterclockwise wires along a longitudinal direction of the central wire line, an auxiliary wire line which is a single line having a diameter smaller than that of the main wire line and extends in a longitudinal direction of the main wire line, and an outermost wire which winds the auxiliary wire line so as to bind the auxiliary wire line and the main wire line.

Abstract: A display device includes a data line, a timing controller configured to apply a transmission signal corresponding to data bits to a data line during an active period in which the data bits are transmitted and apply a transmission clock signal to the data line during a blank period in which the data bits are not transmitted, and a data driver configured to sample the transmission signal (hereinafter, a reception signal) applied through the data line to recover the data bits and drive a display panel according to the recovered data bits. The display device can transmit a clock signal through the data line during the blank period.

Abstract: An LDMOS device and a method for fabricating the same that may include a first conductivity-type semiconductor substrate having an active area and a field area; a second conductivity-type deep well formed on the first conductivity-type semiconductor substrate; a second conductivity-type adjusting layer located in the second conductivity-type deep well; a first conductivity-type body formed in the second conductivity-type deep well; an insulating layer formed on the first conductivity-type semiconductor substrate in the active area and the field area; a gate area formed on the first conductivity-type semiconductor substrate in the active area; a second conductivity-type source area formed in the first conductivity-type body; a second conductivity-type drain area formed in the second conductivity-type deep well. Accordingly, such an LDMOS device has a high breakdown voltage without an increase in on-resistance.

Abstract: Embodiments relate to an image sensor. According to embodiments, an image sensor may include a metal interconnection, readout circuitry, a first substrate, an image sensing device, and a second conduction type interfacial layer. The metal interconnection and the readout circuitry may be formed on and/or over the first substrate. The image sensing device may include a first conduction type conduction layer and a second conduction type conduction layer and may be electrically connected to the metal interconnection. The second conduction type interfacial layer may be formed in a pixel interface of the image sensing device.

Abstract: Provided is a mechanically-coupled tuning fork-scanning probe vibrating system, the system including: a tuning fork vibrating due to an AC voltage applied thereto; a scanning probe attached to a side of the tuning fork and vibrating due to the tuning fork; and a contact member contacting a side surface of the scanning probe and adjusting a position of a contact point at which the contact member contacts with the scanning probe, to vary a natural frequency of a combination body in which the tuning fork and the scanning probe are combined with each other.

Abstract: A method for manufacturing a semiconductor device includes can prevent defects of a semiconductor device due to the deterioration of electro migration (EM)/stress migration (SM) properties of the device as a result of metal corrosion and void generation in burying a novolac material. Embodiments can also prevent the generation of fencing in a metal wire structure.

Abstract: A semiconductor device includes a high voltage first conduction type well in a semiconductor substrate, a second conduction type body in the high voltage first conduction type well, a source region in the second conduction type body, a trench in the high voltage first conduction type well, a first isolation oxide, an impurity doped polysilicon film, and a second isolation oxide stacked in the trench in succession, a drain region in the high voltage first conduction type well on one side of the trench, and a polygate on and/or over the high voltage first conduction type well.

Abstract: Embodiments relate to a semiconductor device and a method of manufacturing a semiconductor. In embodiments, the method may include a first exposure step of performing an exposure process for forming a first photoresist on a semiconductor substrate at one side of the outside of a trench pattern which will be formed, a first etching step of performing a predetermined dry etching method with respect to the first photoresist, a second exposure step of performing an exposure process for forming a second photoresist at the other side of the outside of the trench pattern, which is a side opposite to the first photoresist, and a second etching step of performing the predetermined dry etching method with respect to the second photoresist.

Abstract: A capacitor with a mixed structure of a Metal Oxide Semiconductor (MOS) capacitor and a Poly-silicon Insulator Poly-silicon (PIP) capacitor includes a substrate and a diffusion junction region formed over the substrate. A high concentration diffusion junction region may be formed in a portion of the diffusion junction region. An oxide layer may be formed over the substrate, the oxide layer having an opening that exposes a portion of the high concentration diffusion junction region. A first polysilicon plate may be formed over a portion of the oxide layer and spaced from the opening, and a nitride layer may be formed over a portion of the first polysilicon plate. A sidewall may be formed over a side of the first polysilicon layer, over a side of the nitride layer, and over a portion of the oxide layer between the side of the polysilicon layer and the opening. A second polysilicon plate may be formed over the nitride layer, over the sidewall, and over the high concentration diffusion junction region.

Abstract: A method of forming a CMOS image sensor and a CMOS image sensor. A method of forming a CMOS image sensor may include forming a plurality of photodiodes on and/or over a semiconductor substrate at regular intervals, forming an interlayer insulating film on and/or over an entire surface of a semiconductor substrate including photodiodes, coating an organic compound on and/or over an entire surface of an interlayer insulating film, coating photoresist on and/or over an organic compound, subjecting a photoresist to exposure and/or development to form a photoresist pattern which may expose an interlayer insulating film opposite to a photodiode region, selectively etching a portion of an exposed interlayer insulating film using a photoresist pattern as a mask, and/or removing a photoresist pattern.

Abstract: Provided is a method for setting a security channel between an OLT and at least one ONU in an EPON. In detail, a channel is generated by which the OLT makes a reciprocal security capability agreement with the ONU that wants to set a security channel in a discovery interval and then automatically registers the ONU with the security capability agreement. The security channel is set by which the OLT distributes an encryption key for the security with the ONU completed with the security capability agreement. A renewal point of the encryption key is shared by transmitting a message indicative of a time to change the encryption key between the OLT and the ONU both completed with the encryption key distribution.

Abstract: An image sensor may include a first substrate having circuitry including wires and a silicon layer formed on and/or over the first substrate to selectively contact the wires. The image sensor may include photodiodes bonded to the first substrate while contacting the silicon layer and electrically connected to the wires. Each unit pixel may be implemented having complicated circuitry without a reduction in photosensitivity. Additional on-chip circuitry may also be implanted in the design.

Abstract: A bandgap reference voltage generating circuit, includes: at least two bipolar transistors; an operational amplifier; a first PMOS transistor; and a second PMOS transistor whose source is connected to the upper limit power supply voltage and which supplies the reference current to the bipolar transistors. Further, the bandgap reference voltage generating circuit includes a third PMOS transistor whose source is connected to the upper limit power supply voltage; a fourth PMOS transistor whose source is connected to the upper limit power supply voltage and gate is connected to a drain of the third PMOS transistor; a first NMOS transistor whose source is connected to the lower limit power supply voltage and drain is connected to a drain of the fourth PMOS transistor; and a second NMOS transistor whose drain is connected to the operational amplifier and gate is connected to the drain of the first NMOS transistor.