Abstract: A method for fabricating a semiconductor device is disclosed. The method includes: forming a photoresist film on a semiconductor substrate including a silicide forming region and non-silicide forming region; forming a photoresist pattern as a non-salicide pattern by patterning the photoresist film, so as to cover the non-silicide forming region and open the silicide forming region, with an overhang structure that a bottom is removed more compared to a top; forming a metal film on a top of the photoresist pattern and overall the semiconductor substrate in the silicide forming region; stripping the photoresist pattern and the metal film on the photoresist pattern; and forming a silicide metal film by annealing the metal film remaining on the semiconductor substrate. Therefore, the present invention simplifies a salicide process of a semiconductor device, making it possible to improve yields.

Abstract: Provided is a detection apparatus of Raman scattering and light scattering, and more particularly, a simultaneous detection apparatus of Raman scattering and dynamic light scattering and a detection method using the same. The simultaneous detection apparatus of Raman scattering and light scattering includes: a detection unit for applying incident light to a sample, and detecting Raman scattering in 90° or 180° geometry and light scattering in 90° or 180° geometry in order to simultaneously collect Raman scattering and light scattering; and a computer connected to the detection unit to obtain at least one of the size and distribution of particles from the detected light scattering, and to obtain information of the molecular structure from the detected Raman scattering.

Abstract: A highly foamed coaxial cable having an inner conductor disposed in the cable, a foamed insulator having porous cells surrounding the inner conductor, an outer conductor surrounding the insulator, and a sheath surrounding the outer conductor and the insulator, wherein the total area of macro cell which has a diameter of at least 300/M is larger than the total area of micro cell which has a diameter smaller than 300/M at cross section of cable.

Abstract: A semiconductor device includes an interlayer insulating layer including a plurality of trenches connecting to a number of via holes formed on a semiconductor substrate including lower interconnections, wherein widths of the trenches are greater than widths of the via holes, and metal interconnections formed by burying metal thin films in the via holes and the trenches. Depths of the trenches are adjusted differently from each other depending on required resistances of the metal interconnections.

Abstract: Disclosed are an apparatus and a method for manufacturing an absorption pad used for picking up a package or a strip during a semiconductor manufacturing process. The apparatus includes a workpiece transfer device on which a workpiece is mounted, a laser generator installed above the workpiece transfer device while being spaced apart from the workpiece transfer device by a predetermined distance, a driving unit for moving the workpiece transfer device and the laser generator relative to each other, and a controller for controlling the laser generator. It is possible to precisely form patterns having various sizes and shapes according to use of the absorption pad and the size of the package. Processing conditions for the workpiece are standardized, so that the processing time and manufacturing cost for the absorption pad are minimized.

Abstract: An operational amplifier capable of suppressing power consumption and noise generation includes an offset modifier including a differential amplification circuit, and an offset memory for storing an offset voltage using a latch circuit. The differential amplification circuit includes first and second NMOS transistors connected to an input terminal, first and second PMOS transistors respectively connected to drains of the first and second NMOS transistors, a third NMOS transistor connected to sources of the first and second NMOS transistors, a third PMOS transistor connected to a source of the second PMOS transistor, a fourth NMOS transistor connected to the third PMOS transistor, to form an output to be applied to the offset memory, and left and right modification blocks each connected to an associated one of the first and second NMOS transistor in parallel.

Abstract: Disclosed herein is a gear for eliminating backlash. The gear includes a rotating shaft having a hollow portion. A first gear is connected to an end of the rotating shaft to be rotated in sync with the rotating shaft, and has on a central portion thereof a connecting protrusion which protrudes forwards. A hole is formed so as to communicate with the hollow portion of the rotating shaft, and a pair of first mounting holes is formed in the first gear along an arc thereof. A second gear is rotatably connected to the connecting protrusion of the first gear and has the same teeth as teeth of the first gear. A cylinder is provided in each of the first mounting holes and connected at both ends thereof to the first gear and the second gear, thus rotating the second gear in one direction. A locking cap is provided on an end of the connecting protrusion of the first gear to prevent the second gear from being eliminated from the first gear.

Abstract: Disclosed is a method for fabricating a lateral double diffused metal oxide semiconductor (LDMOS) transistor, which includes implanting impurity ions onto a semiconductor substrate to form a drift region and a body region, forming a photoresist pattern to expose a region where an insulating oxide film is to be formed on the semiconductor substrate, implanting first impurity ions through the photoresist pattern to form a first impurity region, where the insulating oxide film is to be formed, in the semiconductor substrate, forming an insulating oxide film and an outer insulating oxide film on the semiconductor substrate by an oxidation process, and forming a gate electrode on the semiconductor substrate.

Abstract: The present invention relates to a wireless charger for a mobile communication terminal, which allows charging a plurality of batteries in a conveniently way without any terminal connection of the batteries to chargers for various mobile communication terminals such as a cellular phone and PDA and also allows intercepting electromagnetic waves while the charger is used, by means of Faraday's law. The wireless charger of the present invention includes a charger body having an electromagnetic wave intercepting means; a charging pad received in the charger body; and at least one battery that is to be charged by means of induced electromotive force generated by the charging pad, wherein the charger body includes a power supply means, a housing having a receiver for receiving the charging pad and connected to the power supply means, and a cover hinged to the housing.

Abstract: Disclosed herein is a method of acquiring a reference grating of a three-dimensional measurement system using moiré, wherein the three-dimensional measurement system includes a light source, a projection grating, a grating actuator and a camera, and analyzes the moiré pattern acquired through the camera to measure the shape of the object. The method includes the steps of acquiring an initial reference grating using the light source and the projection grating, confirming whether or not the acquired initial reference grating includes noise through a noise detector, and moving the projection grating through the grating actuator to acquire the next reference grating when the initial reference grating does not include noise and correcting the reference grating when the reference grating includes noise. The method can remove the noise included in the reference grating to improve the accuracy of measurement of an object.

Abstract: Disclosed herein is a laptop-size high-order harmonic generation apparatus using near field enhancement. The laptop-size high-order harmonic generation apparatus using near field enhancement includes a femtosecond laser generator, light transfer means for transferring light output from the femtosecond laser generator, micro patterns formed of metallic thin films and configured to have nano-sized apertures for generating near field enhancement when the light output from the light transfer means passes through the micro patterns, a gas supply unit for supplying inert gas to the light when the light transferred through the light transfer means passes through the micro patterns, and a vacuum chamber for accommodating the micro patterns and the gas supply unit under a vacuum atmosphere.

Abstract: A method for manufacturing a semiconductor device includes sequentially forming an insulating layer and a metal layer over a semiconductor substrate, forming a photoresist pattern over the metal layer and etching the metal layer using the photoresist pattern as an etching mask to form a metal line pattern, subjecting the photoresist pattern to a reflow process to form a photoresist pattern over the metal layer and etching the metal layer using the photoresist pattern as an etching mask to form a metal line pattern, subjecting the photoresist pattern to a reflow process to form a reflowed photoresist pattern surrounding the metal line pattern, forming a metal-insulator-metal (MIM) layer over the semiconductor substrate provided with the reflowed photoresist pattern, and removing the MIM layer arranged over the photoresist pattern and the photoresist pattern.

Abstract: Embodiments relate to semiconductor devices and methods for fabricating semiconductor devices. According to embodiments, a semiconductor device may include a bit line and a bit line bar. The device may also include a precharge controller that may generate a precharge control signal, and NMOS transistors and PMOS transistors to precharge the bit line and the bit line bar in response to the precharge control signal. According to embodiments, a precharge speed of a bit line in a semiconductor device may be improved and an operating cycle time of a memory device may also be improved.

Abstract: A method for manufacturing a flash memory device is capable of controlling a phenomenon in which a length of the channel between a source and a drain is decreased due to undercut. The method includes forming a gate electrode comprising a floating gate, an ONO film and a control gate using a hard mask pattern over a semiconductor substrate, forming a spacer over the sidewall of the gate electrode, forming an low temperature oxide (LTO) film over the entire surface of the semiconductor substrate including the gate electrode and the spacer, etching the LTO film such that a top portion of the source/drain region and a top portion of the gate electrode are exposed, and removing the LTO film present over the sidewall of the gate electrode by wet-etching.

Abstract: Embodiments relate to a single poly type EEPROM and a method for manufacturing an EEPROM. According to embodiments, a single poly type EEPROM may include unit cells. A unit cell may include a floating gate at a side of a control node formed on and/or over a semiconductor substrate having an activation region and a device isolation area, not overlapping a device isolation region but overlapping only a top of the activation region. A select gate may be formed on and/or over a top of the activation region. According to embodiments, a ratio of a capacitance of a control node side to a capacitance of a bit line side may increase, which may improve a coupling ratio. According to embodiments, a junction capacitance may be maximized by not doping the floating gate with an impurity, which may allow for a reduction in chip size by securing design margins.

Abstract: A congestion-resilient link adaptation method is provided. The link adaptation method for selecting any one of modes having mapped transmission parameters includes the steps of: estimating a channel-induced error number indicating the number of channel-induced transmission failures in a current mode and comparing the estimated channel-induced error number with a mode-down threshold; and determining whether the mode-down is performed based on the comparison result. Thus, higher throughput can be achieved without use of additional hardware or protocols.

Abstract: A method of fabricating an image sensor. A method of fabricating an image sensor may include preparing a substrate including a pixel region and/or a logic region having transistors and/or gates. A method of fabricating an image sensor may include forming a first interlayer dielectric film on and/or over a substrate to cover gates. A method of fabricating an image sensor may include forming a first dielectric film to expose an upper surface of at least one gate over a pixel region. A method of fabricating an image sensor may include forming a second interlayer dielectric film over a first interlayer dielectric film and/or dielectric film. A method of fabricating an image sensor may include forming a plurality of contact holes, which may be simultaneously formed over a second interlayer dielectric film. An image sensor may include contacts formed over a second interlayer dielectric film. An image sensor is disclosed.

Abstract: A method of coding a moving picture reduces blocking artifacts. The method includes defining pixel sets S0, S1, S2 around a block boundary, selectively determining a deblocking mode as a default mode or a DC offset mode depending on the degree of blocking artifacts. If the default mode is selected, frequency information is obtained around the block boundary per pixel using a 4-point DCT kernel, for example, a magnitude of a discontinuous component belonging to the block boundary is replaced with a minimum magnitude of discontinuous components belonging to the surroundings of the block boundary in the frequency domain and the replacing step is applied to the spatial domain. If the DC offset mode is selected and a determination is made to perform DC offset mode, the blocking artifacts in a smooth region are removed in the DC offset mode.

Abstract: A method of coding a moving picture reduces blocking artifacts. The method includes defining pixel sets S0, S1, S2 around a block boundary, selectively determining a deblocking mode as a default mode or a DC offset mode depending on the degree of blocking artifacts. If the default mode is selected, frequency information is obtained around the block boundary per pixel using a 4-point DCT kernel, for example, a magnitude of a discontinuous component belonging to the block boundary is replaced with a minimum magnitude of discontinuous components belonging to the surroundings of the block boundary in the frequency domain and the replacing step is applied to the spatial domain. If the DC offset mode is selected and a determination is made to perform DC offset mode, the blocking artifacts in a smooth region are removed in the DC offset mode.

Abstract: A method of coding a moving picture reduces blocking artifacts. The method includes defining pixel sets S0, S1, S2 around a block boundary, selectively determining a deblocking mode as a default mode or a DC offset mode depending on the degree of blocking artifacts. If the default mode is selected, frequency information is obtained around the block boundary per pixel using a 4-point DCT kernel, for example, a magnitude of a discontinuous component belonging to the block boundary is replaced with a minimum magnitude of discontinuous components belonging to the surroundings of the block boundary in the frequency domain and the replacing step is applied to the spatial domain. If the DC offset mode is selected and a determination is made to perform DC offset mode, the blocking artifacts in a smooth region are removed in the DC offset mode.