Abstract: An isolated high voltage p-type DMOS transistor comprises a layer of p-type semiconductor material in which a first n-well is disposed. A first annular p-type region is disposed in the first n-well. A first annular shallow trench isolation region is spaced apart from the first annular p-type region. An annular p-well region is spaced apart from the first shallow trench isolation region. An inner perimeter of the annular p-well region is disposed outside of the first annular p-type region. A second annular p-type region is disposed in the p-well. An annular gate has an inner perimeter aligned with the outer perimeter of the first annular p-type region and an outer perimeter disposed over the first shallow trench isolation region. A second annular n-well region is disposed outside of a second annular shallow trench isolation region. The second annular shallow trench isolation region is disposed outside of the annular p-well region.

Abstract: A method for providing color to a stereolithographically produced model is disclosed. This method comprises obtaining data representing the model, such that the data is readable by a stereolithographic model generating machine for solidifying layers of a liquid resin in a vat creating resin layers to create successive cross sections of the model. Each of the resin layers are exposed with energy effective for solidifying the resin. One or more portions of at least one of the resin layers are overexposed with an energy according to a coloring or shading indicated in the data. The model is heated with an effective amount of heat to induce a color or shading change in substantially only the overexposed portions of the model. The model is removed from the vat and cleaned. Next, the model can be exposed to an energy source, followed by the finishing of the model.

Abstract: A method for determining the number of redundancy units to employ in a memory integrated circuit. The critical areas for faults on each process layer in the integrated circuit for a range of defect sizes, and the signatures of the electrical responses of faulted circuits to input test stimuli are determined. A statistical frequency distribution for both the signatures for a ratio of defect sizes on each of the process layers, and for the occurrences of selected combinations of the signatures are determined. A ratio of the signature distribution for different numbers of redundancy units, and the die area for each of the different numbers of redundancy units are determined. The number of usable die per wafer is determined from the signature distribution and the die area. A level of redundancy that maximizes the number of usable die per wafer is selected.

Abstract: A digital splint has a base, a bracket, an access shaft, and a secure shaft. The base is configured to support a digit and the base has a length greater than its width. The bracket can be coupled to the base. The bracket has a first, second, and third walls. The second and third walls extend outward from the first wall. The access shaft is in the first wall and is disposed to receive a skin-penetrating device. The secure shaft is located within the first wall and is disposed at an angle to the access shaft. The secure shaft is coupled to the access shaft and is disposed to secure the skin-penetrating device through the access shaft.

Abstract: An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a third set of routing conductors, in addition to a first set of routing conductors and a second set of routing conductors and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive tertiary input signals as well as regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the first FPGA tile, and provide input signals to the third set of input ports of the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column.

Abstract: A resilient road sign comprising a rigid center member having left and right wings resiliently attached to the center member. The left and right wings are comprised of a substantially rigid material. The left and right wings and the rigid center portion each have a front surface and a rear surface. The left and right wings and rigid center portion may all have written indicia on the front surfaces thereof.

Abstract: An OTP bit cell includes a latch circuit of cross-coupled inverters. A floating gate PMOS transistor is inserted in each of the inverters. One or the other of the floating gate PMOS transistors is programmed through an included programming circuit so that a differential output of the latch circuit provides a corresponding logic state that is the same each time when read. To program a selected floating gate PMOS transistor, appropriate write inputs are applied to the programming circuit while a high reference voltage to the OTP bit cell is raised to a level such that the selected floating gate PMOS transistor is programmed.

Abstract: A storage pixel sensor disposed on a semiconductor substrate comprises a capacitive storage element having a first terminal connected to a fixed potential and a second terminal. A photodiode has an anode connected to a first potential and a cathode. A semiconductor reset switch has a first terminal connected to the cathode and a second terminal connected to a reset potential. A semiconductor transfer switch has a first terminal connected to the cathode and a second terminal connected to the second terminal of the capacitive storage element. A semiconductor amplifier has an input connected to the capacitive storage element and an output. The semiconductor reset switch and the semiconductor transfer switch each have a control element connected to a control circuit for selectively activating the semiconductor reset switch and the semiconductor transfer switch.

Abstract: Medical conditions are treated by administering a therapeutically effective amount of exo-S-mecamylamine or a pharmaceutically acceptable salt thereof, substantially free of its exo-R-mecamylamine, said amount being sufficient to ameliorate the medical condition. The medical conditions include substance addiction (involving nicotine, cocaine, alcohol, amphetamine, opiate, other psychostimulant and a combination thereof), Tourette's Syndrome, and neuropsychiatric disorders (such as bipolar disorder, depression, an anxiety disorder, schizophrenia, a seizure disorder, Parkinson's disease and attention deficit hyperactivity disorder).

Abstract: The disclosed device is directed towards an illumination headgear. The illumination headgear comprises a crown having a lower edge. A brim is disposed on the crown proximate to the lower edge. The brim has a rim disposed along the perimeter of the brim distal from the lower edge. An array of contiguous light emitting diodes is integral within the brim and proximate to said rim. The array of contiguous light emitting diodes is focused to form a contiguous beam.

Abstract: An output buffer switch-on control circuit includes several transistors and a discharge current control circuit. A first transistor has a first terminal connected to an internal voltage line and is controlled by an output data source. A second transistor has a first terminal connected to the internal voltage line and is controlled by a second terminal of the first transistor. The second transistor also has a second terminal connected to a first terminal of an output capacitor. A third transistor is controlled by the output data source and has a first terminal connected to a common voltage. A fourth transistor is digitally controlled and has a first terminal connected to the second terminal of the second transistor. The fourth transistor also has a second terminal connected to the common voltage. The discharge current control circuit is preferably actively-controlled and is connected between a second terminal of the first transistor and a second terminal of the third transistor.

Abstract: The plastic film electrostatic adsorption apparatus of the present invention comprises an electrostatic adsorption electrode, an insulated dielectric layer that covers the electrostatic adsorption electrode and has a center line average roughness of an adsorption surface on which a plastic film is placed of 0.5 micrometers or less, and a power supply electrode that applies a voltage to the electrostatic adsorption electrode. According to this plastic film electrostatic adsorption apparatus, surface treatment can be performed even in a vacuum without requiring tedious work such as application or removal of adhesive. In addition, even if the plastic film expands and deforms due to heat treatment and plasma treatment performed during surface treatment, there is no occurrence of wrinkling, deformation or separation in the plastic film due to the difference in thermal expansion between the electrostatic adsorption surface and plastic film.

Abstract: A method for storing digital information from an image sensor comprises the steps of providing an image sensor producing three-color output data at each of a plurality of pixel locations; providing a digital storage device coupled to the image sensor; sensing three-color digital output data from the image sensor; and storing said three-color output data as digital data in the digital storage device without performing any interpolation on the three-color output data. The data may be compressed prior to storage and expanded after retrieval from storage. In a preferred embodiment, the image sensor comprises a triple-junction active pixel sensor array.

Abstract: A field-programmable gate array (FPGA), comprising: a first FPGA tile, the first FPGA tile comprising a plurality of functional groups (FGs), a regular routing structure, and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive regular input signals, perform a logic operation, and generate regular output signals. The regular routing structure is coupled to the FGs and configured to receive the regular output signals, route signals within the first FPGA tile, and provide the regular input signals to the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the regular routing structure and configured to transfer signals from the regular routing structure to outside of the first FPGA tile.

Abstract: A vertical color filter detector group according to the present invention is formed on a semiconductor substrate and comprises at least six layers of alternating p-type and n-typed doped regions. PN junctions between the layers operate as photodiodes with spectral sensitivities that depend on the absorption depth versus wavelength of light in the semiconductor. Alternate layers, preferably the n-type layers, are detector layers to collect photo-generated carriers, while the intervening layers, preferably p-type, are reference layers and are connected in common to a reference potential referred to as ground. Each detector group includes a blue-sensitive detector layer at an n-type layer at the surface of the semiconductor, a green-sensitive detector layer at an n-type layer deeper in the semiconductor, and a red-sensitive detector layer at the n-type layer deepest in the semiconductor.

Abstract: A method and system for verifying router configuration transactions carried out by a centralized information provider or database system. The centralized database provides verification registration and verification unregistration for various router subsystems associated with said database system. The centralized database and the subsystems registered for verification engage in a verification handler sequence to verify proposed router configuration transactions.

Abstract: A method and apparatus for significantly reducing the number and types of non-volatile memory used on a typical motherboard is disclosed. While there are typically three or more types of non-volatile memory used to support the CPU during system boot and initialization, the present invention uses only one. This allows for a significant savings in materials cost and design effort.

Abstract: In a first embodiment, programming pulses of about 0.25 mA to about 0.5 mA are applied to an amorphous carbon based antifuse in first and second directions for 10 us to form an antifuse link having a finite resistance of less than 2000 ohms. Soaking pulses of about 2 mA to about 5 mA are then applied to the amorphous carbon antifuse in first and second directions for 1 ms and then repeated up to four more times to form an antifuse link with a finite resistance of about 100 ohms to about 400 ohms. In a second embodiment, programming pulses of about 0.25 mA to about 0.5 mA are applied to an amorphous carbon based antifuse in first and second directions for 1 ms and then repeated four more times to form an antifuse link having a finite resistance of less than 2000 ohms.

Abstract: The present system comprises a device and a method for increasing the performance and utilization in a field programmable gate array (FPGA). The device of the present system comprises an FPGA having logic clusters, wherein each logic cluster further comprises a buffer. The method of the present system comprises a method of determining which buffers situated in each logic cluster are located in the best position in the post-placement user netlist to decrease the capacitance in the user netlist.

Abstract: The disclosed device is directed towards an active audio speaker system having at least one audio speaker and an amplifier electrically coupled thereto. The active audio speaker system includes a cabinet having an enclosure defining an interior of the cabinet and an exterior of the cabinet. The interior contains the amplifier. A cooling unit is contiguous with the enclosure of the cabinet. The cooling unit includes a conduction module thermally coupled to the amplifier and a forced convection module at the exterior. The forced convection module is configured to transfer thermal energy from the conduction module.