Abstract: A semiconductor package includes a die that is interposed, flip-chip style, between an upper lead frame and a lower lead frame. The lower lead frame has contacts that are aligned with terminals on the bottom surface of the die. The upper lead frame contacts a terminal on the top side of the die, and the edges of the upper lead frame are bent downward around the edges of the die, giving the upper lead frame a cup shape. The edge of the upper lead frame contact another portion of the lower lead frame, so that all of the contacts of the package are coplanar and can be surface-mounted on a printed circuit board. The terminals of the die are electrically connected to the lead frames by means of solder layers. The thicknesses of the respective solder layers that connect the die to the lead frames are predetermined to optimize the performance of the package through numerous thermal cycles. This is done by fabricating the lower lead frame with a plurality of mesas and using a double solder reflow process.

Abstract: An alignment target includes periodic patterns on two elements. The periodic patterns are aligned when the two elements are properly aligned. By measuring the two periodic patterns at multiple polarization states and comparing the resulting intensities of the polarization states, it can be determined if the two elements are aligned. A reference measurement location may be used that includes third periodic pattern on the first element and a fourth periodic pattern on the second element, which have a designed in offset, i.e., an offset when there is an offset of a known magnitude when the first and second element are properly aligned. The reference measurement location is measured at two polarization states. The difference in the intensities of the polarization states at reference measurement location and is used to determine the amount of the alignment error.

Abstract: A trench-gated MOSFET includes adjacent mesas formed on opposite sides of a trench. A body region in the first mesa extends downward below the level of the trenches and laterally across the bottom of the trenches. The body region in the second mesa extends part of the way down the mesa, leaving a portion of the drain abutting the trench. The body region in the second mesa includes a channel region adjacent a wall of the trench. The area where the drain abuts the trench is thus relatively restricted and the drain-gate capacitance of the device is reduced. Moreover, the drain-gate capacitance is made independent of the depth and width of the trenches, allowing greater freedom in the design of the MOSFET.

Abstract: When substantially all features in a layout for a layer of material in an integrated circuit (IC) are defined using a phase shifting mask, the related complementary mask that is normally used to define the remaining features and edges can be improved if intensities in an aerial image from openings on the complementary mask that are below threshold are increased to ensure that each opening meets or exceeds threshold. Such increase of intensities improves effectiveness of critical openings that are otherwise too small to print. Absent intensity increase, such openings could limit the application of optical lithography using phase shifting masks to ever shrinking technologies. The intensities are increased in some embodiments by enlarging some openings in the complementary mask in directions not constrained by features to be formed in an integrated circuit (by use of the phase shifting mask).

Abstract: A lifecycle analyzer includes a temperature control element for controlling the temperature of a plurality of magnetoresistive (MR) elements, which may be, e.g., in bar, slider, head gimbal assembly, or head stack assembly form. The MR elements are in electrical contact with a stress probe element for applying a bias voltage or current stress. The MR elements and/or a magnetic field generator are moved to place one or more MR elements within the magnetic field of the magnetic field generator for testing. During testing, the MR elements are in electrical contact with a test probe element. The temperature of the MR elements may be controlled during both the stressing and testing.

Abstract: An alignment target includes periodic patterns on two elements. The alignment target includes two locations, at least one of which has a designed in offset. In one embodiment, both measurement locations have a designed in offset of the same magnitude but opposite directions. For example, two separate overlay patterns that are mirror images of each other may be used. Alternatively, the magnitudes and/or directions may vary between the measurement locations. The radiation that interacts with the measurement locations is compared. The calculated difference is extremely sensitive to any alignment error. If the difference between the patterns is approximately zero, the elements are properly aligned. When an alignment error is introduced, however, calculated difference can be used to determine the error. In one embodiment, the alignment target is modeled to determine the alignment error. In another embodiment, additional overlay patterns with additional reference offsets are used to determine the alignment error.

Abstract: A computer is programmed to fit exponential models to upper percentile subsets of observed measurements for performance metrics collected as attributes of a computer system. The subsets are defined from sets chosen to reduce model bias due to expected variations in system performance, e.g. those resulting from temporal usage patterns induced by end users and/or workload scheduling. Measurement levels corresponding to high cumulative probability, indicative of likely performance anomalies, are extrapolated from the fitted models generated from measurements of lower cumulative probability. These levels are used to establish and to automatically set warning and alert thresholds which signal to (human) administrators when performance anomalies are observed.

Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.

Abstract: A repository contains multiple versions of an object, and any version of the object can be modified by a user, as and when necessary. A table for one object (“first object”) that is contained in another object (“second object”) has at least two columns, namely one column for a minimum version of the second object and another column for a maximum version of the second object. If a number of versions of the first object are responsive to a query, then one version of the first object is selected if a version of the second object that is responsive to the query happens to be in the range defined by the just-described minimum version number and the maximum version number. Depending on the embodiment, the second object can be an immediate parent of the first object, or can be an ancestor (also called “first class object”) of the first object that is not contained in any other object.

Abstract: A semiconductor package contains a metal leadframe that has been specially treated by roughening it with a chemical etchant. The roughening process enhances the adhesion between the leadframe and the molten plastic during the encapsulation of the leadframe and thereby reduces the tendency of the package to separate when exposed to moisture and numerous temperature cycles. In one embodiment, the leadframe made of copper is roughened with a chemical etchant that contains sulfuric acid and hydrogen peroxide.

Abstract: Every function that is called (“called function”) is expanded by insertion of several statements at the entry and exit thereof. Moreover, a calling function may also be expanded, by insertion of statements prior to and/or subsequent to a statement in which a called function is invoked. Many of the statements that are inserted contain new variables (called “synthetic variables”) to which registers are allocated during register allocation; the synthetic variables are not part of the originally-written software but are introduced during expansion, e.g. to transfer arguments to and return value from the called functions. Statements that are inserted can be either statements that are translated into assembly code in the normal manner, or alternatively dummy statements that contain instructions which are never translated into assembly code (i.e. ignored by the assembler. Use of dummy statements ensures that a web is established for new variables. After expansion, register allocation is performed.

Abstract: A model of a sample with one or more films that overlie a complicated structure can be produced using a first portion that models the physical characteristics of the film(s) and a second portion that does not attempt to model the physical characteristics of the underlying structure, but instead models the affect of the underlying structure on incident light. By way of example, the second portion of the model may use a one-dimensional periodic pattern to model a complicated two-dimensional periodic pattern. A characteristic, such as thickness, of the film(s) may be measured using the model. The results may be verified by the linear relationship of ratios between a plurality of measured locations on the sample and associated locations on the sample that do not have the underlying structures.

Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.

Abstract: A new instance of an application is added to a group of existing instances (of that application) that share a resource, such as a database. The new instance is added by creating a new object for the new instance by cloning an existing object of an existing instance in the group, setting up connectivity between the new instance and a network through which the multiple instances communicate with one another, and starting up the new instance. The just-described acts are performed in the reverse order when deleting an existing instance. Each of these acts may be performed manually, or automatically without user input, with the user issuing at least one instruction to add or delete an instance.

Abstract: A digital image upscaling system enhances the visual quality of enlarged images by detecting diagonal edges and applying an appropriate scaling algorithm, such as a rotated bilinear scaling process, to output pixels associated with those edges. The rotated bilinear scaling process involves detecting diagonal edges and specifying a new frame of reference rotated 45° from the original frame of reference, and then selecting a rotated pixel set based on the new frame of reference. Bilinear interpolation in the new frame of reference using the rotated pixel set provides improved pixel data for the output pixel. Output pixels found not to be associated with diagonal edges are processed using standard bilinear interpolation.

Abstract: An apparatus and method write data to a storage medium, and subsequently automatically refresh the data to avoid loss of the data due to spontaneous thermal degradation. The apparatus and method may check whether an indicator (also called “refresh indicator”) if saved contemporaneous with writing of the data satisfies a predetermined condition indicating that the data needs to be refreshed. If so, a “refresh” operation is performed, wherein the to-be-refreshed data is read from and written back to the same storage medium. The refresh indicator can be any parameter that indicates a need to refresh the data prior to occurrence of one or more soft errors. In one example, the apparatus and method read the data back contemporaneous with writing of the data, and measure an amplitude of a readback signal and store, as the refresh indicator, a predetermined fraction (e.g. half) of the measured value (i.e., a threshold number). When a current value of the amplitude falls below the stored value, the data is refreshed.

Abstract: An antifuse, which has a programmable material disposed between two conductive elements, is programmed using multiple current pulses of opposite polarity. The first pulse has a current that is insufficient to fully program the antifuse, i.e., produce a desired level of resistance. In one embodiment the first pulse is current limited. The first pulse advantageously drives a conductive filament from one conductive element through the antifuse material, which may be, e.g., amorphous silicon. The conductive filament from the first pulse, however, has a limited cross sectional area. A programming pulse having the same voltage with opposite polarity and a current with increased magnitude is used to drive material from the other conductive element into the antifuse material, which increases the cross sectional area of the conductive filament thereby reducing resistance. Additional programming pulses, as well as current limited pulses, may be used if desired.

Abstract: A processor is programmed to reduce a problem of adding a new connection to a time-space-time (TST) switch of a communication network into a problem of graph theory, and to solve the problem using a heuristic instead of an exact algorithm. A solution, if provided by the heuristic, is used to rearrange the connections in the TST switch. Several embodiments of such a programmed processor reduce a connection rearrangement problem of a TST switch into any one of the NP-complete problems (such as the vertex coloring problem or the boolean satisfiability (SAT) problem). In some such embodiments, the processor is programmed based on the Brélaz heuristic to find a solution to the vertex coloring problem. In other embodiments, other heuristics, such as a genetic algorithm, may be used.

Abstract: A Schottky rectifier includes a rectifying interface between a semiconductor body and a metal layer. Trenches are formed in the surface of the semiconductor body and regions of a conductivity type opposite to the conductivity type of the body are formed along the sidewalls and bottoms of the trenches, the regions forming PN junctions with the rest of the body. When the rectifier is reverse-biased, the depletion regions along the PN junctions merge to occupy the entire width of the mesas. The device is fabricated by implanting dopant directly through the sidewalls and bottoms of the trenches, by filling the trenches with a material containing dopant and causing the dopant to diffuse through the sidewalls and bottoms of the trenches, or by implanting and diffusing the dopant into a gate filling material.

Abstract: Colors to be used in register allocation are grouped into a number of sequences. Each sequence is associated with an attribute (e.g. size and/or type) of variables whose nodes in an interference graph can be colored by colors in the sequence. In certain embodiments, in addition to the above-described grouping, colors within a group are ordered in a sequence. The specific order that is used may depend on, for example, an attribute (such as size) and a predetermined preference. One example of such a predetermined preference is that a color that represents a register of the size that is associated with the sequence is located at the front of the sequence. Another color located later in the sequence represents a register of a different size than the size associated with the sequence.