Patents Represented by Attorney Silicon Valley Patent Group
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Patent number: 7183610Abstract: In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes the “drift” region of the mesa to become depleted, enhancing the ability of the MOSFET to block current. The doping concentration of the drift region can therefore be increased, reducing the on-resistance of the MOSFET. The buried source electrode also reduces the gate-to-drain capacitance of the MOSFET, improving the ability of the MOSFET to operate at high frequencies. The substrate may advantageously include a plurality of annular trenches separated by annular mesas and a gate metal layer that extends outward from a central region in a plurality of gate metal legs separated by source metal regions.Type: GrantFiled: April 30, 2004Date of Patent: February 27, 2007Assignee: Siliconix incorporatedInventors: Deva N. Pattanayak, Yuming Bai, Kyle Terrill, Christiana Yue, Robert Xu, Kam Hong Lui, Kuo-In Chen, Sharon Shi
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Patent number: 7184510Abstract: A differential charge pump includes a transient reducing circuit that provides multiple switching current paths to reduce transients caused by the charge transfer as the charge pump is switched. The differential charge pump includes separate current sources in the transient reducing circuit that are switchably coupled to the non-active current source in the charge pump. In one embodiment, each current sources include a static current source and a variable current source that is controlled by a common mode feedback circuit. The variable current source may produce a current with less magnitude than the current produced by the static current source.Type: GrantFiled: September 26, 2003Date of Patent: February 27, 2007Assignee: Quicklogic CorporationInventor: Soon-Gil Jung
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Patent number: 7176548Abstract: A semiconductor substrate includes a pair of trenches filled with a dielectric material. Dopant introduced into the mesa between the trenches is limited from diffusing laterally when the substrate is subjected to thermal processing. Therefore, semiconductor devices can be spaced more closely together on the substrate, and the packing density of the devices can be increased. Also trench constrained doped region diffuse faster and deeper than unconstrained diffusions, thereby reducing the time and temperature needed to complete a desired depth diffusion. The technique may be used for semiconductor devices such as bipolar transistors as well as isolation regions that electrically isolate the devices from each other. In one group of embodiments, a buried layer is formed at an interface between an epitaxial layer and a substrate, at a location generally below the dopant in the mesa.Type: GrantFiled: August 15, 2005Date of Patent: February 13, 2007Assignee: Advanced Analogic Technologies, IncInventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
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Patent number: 7176982Abstract: A system and system for performing adaptive recursive noise reduction with still pixel detection on a video stream is presented. After processing a field pixels that were modified are stored in the field so that processing of later fields uses the modified pixels. Furthermore, the system uses novel still pixel detection routines that include multiple thresholds and multiple windows of pixels so that noise reduction is only performed on still pixels.Type: GrantFiled: September 9, 2003Date of Patent: February 13, 2007Assignee: Huaya Microelectronics, Ltd.Inventors: Ge Zhu, Edward Chen, Henry Haojan Tung
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Patent number: 7176977Abstract: A method and system for deinterlacing an interlaced video stream is presented. The method and system determines whether an interlaced video stream is a normal mode video stream or a special mode video stream. Special mode video streams, which interlaced video streams created from a progressive original video stream, are deinterlaced using special mode deinterlacing, which involves merging two fields to form a frame. Normal mode video streams are deinterlaced using normal mode deinterlacing, which involves converting a field into a frame using line repeating or some form of interpolation to generate the missing scan lines.Type: GrantFiled: September 9, 2003Date of Patent: February 13, 2007Assignee: Huaya Microelectronics, Ltd.Inventors: Ge Zhu, Qing Yang
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Patent number: 7173417Abstract: A metrology instrument includes an eddy current sensor that is mounted to and concentric with a confocal distance sensor. By measuring the precise vertical placement of the eddy current probe with respect to the surface of the sample using the confocal distance sensor, the accuracy and precision of the eddy current measurement is improved. Because the confocal distance sensor and the eddy current sensor are confocal, there is no need to move the relative lateral positions between the sample and instrument, between the distance measurement and the eddy current measurement, thereby reducing error in the measurement as well are maximizing the throughput by minimizing the required stage travel for a single measurement.Type: GrantFiled: March 28, 2003Date of Patent: February 6, 2007Assignee: Nanometrics IncorporatedInventors: Jaime Poris, Claudio L. Rampoldi, Pablo I. Rovira, Christopher W. Blaufus
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Patent number: 7167486Abstract: The number of holes that are opened in a firewall for internet telephony is limited to a first hole used for call control and a second hole used for audio traffic. Fixed destination ports for telephony traffic and call control traffics are created at a destination. Media streams are received at the telephony fixed destination port. The source of each media stream is commanded to provide a unique identifier for each media stream arriving at the destination from each source. Each media stream is identified by a unique identifier provided by the source. The unique identifier for each media stream is communicated to the destination by each source over call control. All telephony traffic is received only at the fixed destination port or telephony and all call control is received only at the fixed destination port for call control.Type: GrantFiled: January 19, 2001Date of Patent: January 23, 2007Assignee: Shoretel, Inc.Inventors: David Cornelius, Edwin J. Basart
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Patent number: 7161634Abstract: An error diffusion system in accordance with an embodiment of the present invention adjusts the color depth of an RGB signal using error diffusion without the using an expensive frame buffer. Specifically, a color depth adjustment unit in accordance with the present invention can perform error diffusion on an RGB signal using two error buffers, which are smaller in memory size than typical line buffers that would be used for the video stream.Type: GrantFiled: March 6, 2003Date of Patent: January 9, 2007Assignee: Huaya Microelectronics, Ltd.Inventor: Wai Khaun Long
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Patent number: 7162401Abstract: Whenever a resource being modeled is accessed, an indication about the access is stored in a number of memory locations of a corresponding number of applications that are interested in monitoring the resource. The memory locations (also called “monitoring memory locations”) are individually identified for each application when allocating a location in main memory. At this time, a pointer to the monitoring memory location is supplied to the application and also added to a group of pointers of locations to be updated when accessing the resource. In addition, in certain embodiments, a bit is allocated within a bitmap for each monitoring memory location for any given application. Such a bit is set at the time of updating the corresponding monitoring memory location and cleared when the application reads the monitoring memory location. Just checking the bitmap as a whole can inform an application if there is any change in any monitoring memory locations of that application.Type: GrantFiled: March 28, 2003Date of Patent: January 9, 2007Assignee: Applied Micro Circuits CorporationInventor: Robert Emil Abeles
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Patent number: 7161753Abstract: A discrete-track-recording (DTR) disk (also called “patterned” disk) has a sectored servo formed by modulation of its sidewalls in a predetermined manner, whereas sidewalls of data sectors are not modulated in this manner. Each servo sector has two side walls that are each respectively modulated in two different ways. Hence, a readback signal from a given servo sector contains components of each of the two different modulations, even in case of “DC” erase initiation. Therefore, the just-described modulated servo sectors eliminate servowriting. Moreover, data signals are read without filtering the modulation, because data sector sidewalls are not modulated.Type: GrantFiled: January 28, 2005Date of Patent: January 9, 2007Assignee: Komag, Inc.Inventors: David Wachenschwanz, David Treves
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Patent number: 7153724Abstract: A series of grooves are etched in a leadframe to be used in fabricating a group of semiconductor packages at locations where the leadframe will later be sawed to separate the semiconductor packages. In variations of the process, the grooves may be wider or narrower than the kerf of the saw cuts and may be formed on the side of the leadframe facing towards or away from the entry of the saw blade.Type: GrantFiled: August 8, 2003Date of Patent: December 26, 2006Assignee: NS Electronics Bangkok (1993) Ltd.Inventors: Saravuth Sirinorakul, Somchai Nondhasitthichai, Sitta Jewjaitham, Yee Heong Chua
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Patent number: 7144822Abstract: A method for plasma processing of semiconductor wafers is provided that reduces plasma-induced damage to the gate dielectric while limiting damage to the wafer from particulates that flake off of the interior surfaces of the reaction chamber. Plasma conditions are maintained in the reaction chamber while the wafer is transferred into the chamber and the plasma process is performed. After the plasma process, while still maintaining plasma conditions, the wafer is cooled to a removal temperature and removed from the reaction chamber.Type: GrantFiled: February 6, 2002Date of Patent: December 5, 2006Assignee: Novellus Systems, Inc.Inventor: Michael D. Kilgore
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Patent number: 7142223Abstract: A de-interlacing methodology generates frames from interlaced video signals by incorporating data from multiple fields into an interpolation-based de-interlacing process. Pixels directly above and below a blank pixel location and pixels immediately before and after the blank pixel location (in the fields immediately preceding and following, respectively, the blank pixel field) can be used to interpolate a pixel value for the blank pixel location. The use of pixel data from multiple fields improves the resolution of the interpolation process, thereby improving output frame accuracy. Adjacent pixel values can also be adjusted to further improve the consistency of the visual display provided by the output frames.Type: GrantFiled: September 9, 2003Date of Patent: November 28, 2006Assignee: Huaya Microelectronics, Ltd.Inventor: Ge Zhu
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Patent number: 7137775Abstract: A fan array fan section in an air-handling system includes a plurality of fan units arranged in a fan array and positioned within an air-handling compartment. One preferred embodiment may include an array controller programmed to operate the plurality of fan units at peak efficiency. The plurality of fan units may be arranged in a true array configuration, a spaced pattern array configuration, a checker board array configuration, rows slightly offset array configuration, columns slightly offset array configuration, or a staggered array configuration.Type: GrantFiled: March 22, 2004Date of Patent: November 21, 2006Assignee: Huntair Inc.Inventor: Lawrence G. Hopkins
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Patent number: 7135738Abstract: A family of semiconductor devices is formed in a substrate that contains no epitaxial layer. In one embodiment the family includes a 5V CMOS pair, a 12V CMOS pair, a 5V NPN, a 5V PNP, several forms of a lateral trench MOSFET, and a 30V lateral N-channel DMOS. Each of the devices is extremely compact, both laterally and vertically, and can be fully isolated from all other devices in the substrate.Type: GrantFiled: January 28, 2004Date of Patent: November 14, 2006Assignees: Advanced Analogic Technologies, Inc., Advanced Analogic Technologies (Hong Kong) LimitedInventors: Richard K. Williams, Michael E. Cornell, Wai Tien Chan
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Patent number: 7129718Abstract: A structure and a method for measuring the bonding resistance are provided. The structure for measuring a bonding resistance between a first object and a second object is provided, wherein the first object has a plurality of first pins and a reference pin, and the second object has a plurality of second pins corresponding to the plurality of first pins and the reference pin. The structure further includes a first circuit formed by electrically connecting the reference pin to the first pin adjacent to the reference pin in a first direction, and a second circuit formed by electrically connecting a second pin corresponding to the reference pin to the adjacent second pin in a second direction. By connecting the first and the second circuits in series, the value of the bonding resistance is easily measured.Type: GrantFiled: April 27, 2006Date of Patent: October 31, 2006Assignee: Hannstar Display Corp.Inventors: Shu-Lin Ho, Shih-Chieh Wang
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Patent number: 7129177Abstract: During fabrication of a write head via holes are first opened in a gap layer, followed by formation of seed layers instead of the other way around. Moreover a first seed layer is formed, and without the first seed layer being used a second seed layer is formed. The second seed layer (which is the topmost layer) is used in plating to form coils (e.g. of copper) for the write head. After coil formation, the first seed layer is used for plating to form vias (e.g. of NiFe). The two seed layers may be formed in a single operation by using two different targets in a vacuum deposition chamber. Moreover, a single insulation layer is sufficient to insulate and protect all plated elements, regardless of whether they are formed by use of the first seed layer or the second seed layer.Type: GrantFiled: October 29, 2004Date of Patent: October 31, 2006Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventors: Douglas Kei Tak Tsang, Jorge D. Colonia, Yvette Chung Nga Winton, Michael Ming Hsiang Yang
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Patent number: 7118953Abstract: A trench MIS device is formed in a semiconductor die that contains a P-epitaxial layer that overlies an N+ substrate and an N-epitaxial layer. In one embodiment, the device includes a drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. A termination region of the die includes a half-trench at an edge of the die and an N-type region that extends from a bottom of the half-trench to the substrate. An insulating layer and an overlying metal layer extend from the surface of the epitaxial layer into the half-trench. Preferably, the elements of the termination region are formed during the same process steps that are used to form the active elements of the device.Type: GrantFiled: June 1, 2005Date of Patent: October 10, 2006Assignee: Siliconix incorporatedInventor: Mohamed N. Darwish
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Patent number: 7119990Abstract: A head for use in a drive includes a heating element capable of generating heat sufficient to cause the head to have a shape that is similar or identical to the shape that the head has when performing an operation (e.g. writing) on a recording medium in the drive. The heating element is activated when the operation is not being performed. Hence, a head generates the same amount (or similar amount) of heat and is therefore at the same temperature (also called “operating temperature”), regardless of whether or not an operation (such as writing) is being performed. Therefore, the head maintains a fixed shape or has a shape that varies minimally, within a predetermined range around the fixed shape, that in turn results in maintaining fly height (distance between the head and the recording medium). The heating element may be implemented to use loss mechanisms inherent in a write transducer, e.g. by providing a center tap to the write transducer.Type: GrantFiled: February 3, 2003Date of Patent: October 10, 2006Assignee: Komag, Inc.Inventors: Christopher H. Bajorek, Thomas A. O'Dell
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Patent number: 7115858Abstract: A normal incidence reflectometer includes a rotatable analyzer/polarizer, which permits measurement of a diffracting structure. Relative rotation of the analyzer/polarizer with respect to the diffracting structure permits analysis of the diffracted radiation at multiple polarity orientations. A spectograph detects the intensity of the spectral components at different polarity orientations. Because the normal incidence reflectometer uses normally incident radiation and an analyzer/polarizer that rotates relative to the diffracting structure, or vice-versa, the orientation of the diffracting structure does not affect the accuracy of the measurement. Thus, the sample holding stage may use X, Y, and Z, as well as r-? type movement and there is no requirement that the polarization orientation of the incident light be aligned with the grating of the diffraction structure.Type: GrantFiled: September 25, 2000Date of Patent: October 3, 2006Assignee: Nanometrics IncorporatedInventors: James M. Holden, William A. McGahan, Richard A. Yarussi, Pablo I. Rovira, Roger R. Lowe-Webb