Patents Represented by Attorney, Agent or Law Firm Skjerven, Morrill, MacPherson Franklin and Friel
  • Patent number: 6173527
    Abstract: An ozone containing gas is injected into a portion of top soil that was previously oversaturated with water, to stimulate the propagation and growth of living organisms. The injected ozone oxidizes at least one molecule (also called “parent molecule”) in the top soil to create at least one byproduct that is smaller than the parent molecule. The small size of such byproducts allows the byproducts to cause the growth of living organisms (such as plants including fungi and tomatoes). The byproducts can be used to grow a fungi (such as Trichoderma, spp.) that is (1) parasitic to detrimental fungi such as fusarium or is (2) a stimulant for chlorophyll-bearing plants, or is both. The byproducts can also be used to directly grow the chlorophyll-bearing plants. An ozone containing gas can be injected via a soil injector connected to an ozone supplier that is either stationary or is moved over a field, e.g. by a vehicle.
    Type: Grant
    Filed: March 13, 1998
    Date of Patent: January 16, 2001
    Assignee: Soilzone, Inc.
    Inventor: Alan E. Pryor
  • Patent number: 6164118
    Abstract: A calibration disk for calibrating the fly height of a head, includes spaced circumferencial bands on the disk extending in a concentric fashion from adjacent an outer diameter of the disk to near an inner diameter of the disk. Each of the bands include radial and circumferencial spaced asperity emulating bumps having a population sufficient to produce a constant and continuous output signal from a glide head when the glide head flies lower than a maximum height of the bumps. The height of the bumps within individual bands are substantially uniform, and the average heights of the bumps in each band differ from each other. The configuration of the bumps on the calibration disk advantageously avoids errors caused by disk waviness, runout, and contamination. Further, using the differing heights of the bumps on the calibration disk, a glide head can be calibrated on the glide tester without using an independent fly height measurements for the glide head.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: December 26, 2000
    Assignee: Komag Incorporated
    Inventors: Shoji Suzuki, Daryl M. Shiraki, Jayadev P. Patel, Dan Frusescu, David Treves, Tuan H. Hua
  • Patent number: 6167252
    Abstract: A device that broadcasts an electronic serial number, or ESN, is made secure from cloning using one or more of a plurality of measures, including coupling the memory used for storing the ESN more closely to the ESN processor, fabricating the ESN memory as part of the ESN processor, including the ESN memory in another processor and encrypting communications between the other processor and the ESN processor, and comparing multiple copies of the ESN stored in different memories. The later technique is also effective in securing the JTAG port of an ESN processor.
    Type: Grant
    Filed: August 27, 1996
    Date of Patent: December 26, 2000
    Assignee: NEC Electronics, Inc.
    Inventor: Paul E. Cohen
  • Patent number: 6163548
    Abstract: A pilot acquisition unit for code division multiple access (CDMA) communication systems is provided which includes a fast Hadamard transform (FHT) unit and a pre-Hadamard processing unit. The FHT unit determines the quality, in accordance with a metric, of each of a set of possible pseudo-random number (PN) loadings and the pre-Hadamard processing unit generates a vector u per set of PN loadings. The vector u defines a quality metric of a received pilot signal with the set of possible PN loadings, the pre-Hadamard processing unit providing the vector u to the FHT unit.
    Type: Grant
    Filed: June 5, 1997
    Date of Patent: December 19, 2000
    Assignee: D.S.P.C. Technologies Ltd.
    Inventors: Doron Rainish, David Ben-Eli, David Burshtein, Shlomo Shamai
  • Patent number: 6163492
    Abstract: A non-volatile programmable latch (210) has a fuse (F1) connected between a non-ground voltage terminal (212) and an output terminal (OUT). A NMOS transistor (110) is connected between the output terminal and ground. An inverter (120) has an input connected to the output terminal and an output connected to the gate of the NMOS transistor. A diode connects the output terminal to the non-ground voltage terminal (212) to prevent a charge build up on the output terminal when the power is off.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: December 19, 2000
    Assignee: Mosel Vitelic, Inc.
    Inventors: Nikolas Sredanovic, Helena Calendar
  • Patent number: 6159354
    Abstract: An apparatus for depositing an electrically conductive layer on the surface of a wafer comprises a flange. The flange has a cylindrical wall and an annulus attached to a first end of the cylindrical wall. The annulus shields the edge region of the wafer surface during electroplating reducing the thickness of the deposited electrically conductive layer on the edge region. Further, the cylindrical wall of the flange can be provided with a plurality of apertures adjacent the wafer allowing gas bubbles entrapped on the wafer surface to readily escape.
    Type: Grant
    Filed: November 13, 1997
    Date of Patent: December 12, 2000
    Assignees: Novellus Systems, Inc., International Business Machines, Inc.
    Inventors: Robert J. Contolini, Jonathan Reid, Evan Patton, Jingbin Feng, Steve Taatjes, John Owen Dukovic
  • Patent number: 6157123
    Abstract: A flat panel display contains a faceplate structure (174 or 350), a backplate structure (175 or 351), and a spacer (140, 340, 0r 341). A light-emitting structure (171 or 306) is located along a faceplate (170 or 302) in the faceplate structure. An electron-emitting structure (172 or 305) is located along a backplate (173 or 303) in the backplate structure. The spacer is situated between the light-emitting and electron-emitting structures. Transition metal oxide or transition metal in oxide state is present in a ceramic core (401, 501, 0r 601) or/and a resistive skin (402, 403, 502, 503, 602, or 603) of the spacer.
    Type: Grant
    Filed: February 26, 1999
    Date of Patent: December 5, 2000
    Assignee: Candescent Technologies Corporation
    Inventors: Anthony P. Schmid, Christopher J. Spindt, David L. Morris, Theodore S. Fahlen, Yu Nan Sun
  • Patent number: 6157039
    Abstract: A charged particle beam column efficiently illuminates a blanking aperture array by splitting a charged particle beam into multiple charged particle beams and focusing each charge particle beam on a separate aperture of the blanking aperture array. Where an electron source with a small effective source size is used, for example an electron field emission source or Schottky source, crossovers of the individual beams may occur within the separate apertures of the blanking aperture array. Consequently, no demagnification of the beams passing through the blanking aperture array is necessary to form a small exposure pixel on the writing plane. Thus, for example, electron-electron interactions are minimized, thereby increasing throughput of the system. Further, undesirable scattering of the charged particle off the edge or sidewall of the apertures of the blanking aperture array is avoided.
    Type: Grant
    Filed: May 7, 1998
    Date of Patent: December 5, 2000
    Assignee: Etec Systems, Inc.
    Inventor: Marian Mankos
  • Patent number: 6154064
    Abstract: A sense amplifier having four NMOS transistors and two resistors is operable at voltage supplies less than 2.5 volts and has a fast response time. The drain terminals of two of the NMOS transistors, each receiving an input voltage signal at its gate terminal, provide a differential output voltage signal across the two resistors. The source terminals of these two NMOS transistors are coupled to the drain and gate terminals of a cross-coupled second pair of NMOS transistors. The amplifier exhibits negative input capacitance at each of its input terminals. The amplifier has a common mode input voltage that is substantially equal to the common mode output voltage, facilitating the cascading of many stages of the amplifier. Each stage of a multi-stage cascade of the amplifiers has a greater than unity voltage gain if driving a low capacitance line or a smaller than unity gain if driving a high capacitance line.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: November 28, 2000
    Inventor: Robert J. Proebsting
  • Patent number: 6154386
    Abstract: A memory device includes a plurality of bit lines, with each bit line serving at least one respective memory cell. A plurality of input/output lines are connected and parallel to the bit lines. The input/output lines allow data to be placed upon or extracted from the bit lines. Because the I/O lines are positioned parallel, rather than perpendicular, to the bit lines, the surface area required to implement the memory device does not increase in proportion to the number of bit lines provided. Accordingly, a relatively wide data path can be implemented on the memory device without significantly increasing the amount of surface area.
    Type: Grant
    Filed: June 16, 1998
    Date of Patent: November 28, 2000
    Assignee: G-Link Technology
    Inventor: Adrian E. Ong
  • Patent number: 6150805
    Abstract: A method and circuits for generating a start-up signal to force a bistable reference circuit into a conducting state. The start-up signal ensures that the reference circuit operates to provide a desired output signal when power is applied. The start-up signal is self-generated and self-canceled, rather than relying on an externally supplied pulse, and is input to the reference circuit via a hysteresis circuit (e.g., Schmitt inverter).
    Type: Grant
    Filed: November 6, 1998
    Date of Patent: November 21, 2000
    Assignee: Fairchild Semiconductor Corporation
    Inventor: A. Karl Rapp
  • Patent number: 6149326
    Abstract: A tape cartridge for a debossing stamper includes a casing, a tape-containing supply spool and a tape take-up spool in the casing, the supply spool having at least one reflector pad visually accessible from the exterior of the casing by an optical reflective sensor for detecting and indicating an amount of tape remaining on the supply spool. In one embodiment the at least one reflector pad is a series of equally spaced reflector pads on an outer periphery of the supply spool. The sensor provides a feedback on each 1/4 revolution of said supply reel, the feedback being received by firmware to track the number of motor steps to drive the take-up spool and to rotate the supply spool a 1/4 turn, and wherein a computer calculates the amount of tape remaining on the supply spool based on supply spool core diameter, take-up spool core diameter and total tape length.
    Type: Grant
    Filed: April 13, 1998
    Date of Patent: November 21, 2000
    Assignee: Taurus Impressions, Inc.
    Inventors: Charles T. Groswith, III, William A. Banks, Eugene F. Duval, Roger M. Gray, Raymond D. Heistand, II, Barry C. Kockler, Warren K. Shannon, Robert E. Smith, William J. Usitalo
  • Patent number: 6150962
    Abstract: A predictive data entry method permits a user of a device to efficiently enter data using a keypad where each of a plurality of keys represents a plurality of different characters. When the user presses one of the keys representing multiple characters, the predictive data entry method determines the character within the multiple characters most likely desired by the user. Thus, in most instances, a single key stroke is sufficient to select the desired character.
    Type: Grant
    Filed: June 14, 1999
    Date of Patent: November 21, 2000
    Assignee: Phone.com, Inc.
    Inventor: Alain S. Rossmann
  • Patent number: 6149512
    Abstract: A linear pad conditioning mechanism provides a linear in situ or ex situ conditioning for a polishing pad mounted on a polishing belt of a CMP apparatus. The linear pad conditioning mechanism includes a linear oscillation mechanism for driving a conditioning pad in a direction orthogonal to the polishing belt's direction of travel. In one example, multiple conditioning assemblies are provided to each provide a trapezoidal conditioning pad, and the conditioning assemblies are positioned such that a constant-width area in the polishing belt's direction of travel is provided. In that example, a rotational mechanism is provided to position the conditioning pad between a conditioning position against the polishing pad, and a cleaning position in a bath of cleaning fluid. Further, each conditioning assembly is provided a fluid delivery system to a conditioner block, so that a conditioner fluid can be delivered at the point of use.
    Type: Grant
    Filed: November 6, 1997
    Date of Patent: November 21, 2000
    Assignee: Aplex, Inc.
    Inventors: Ethan C. Wilson, H. Alexander Anderson, Gregory Appel
  • Patent number: 6150661
    Abstract: An absorption spectroscopy device for determining the concentration of a gas (such as oxygen) in a sample cell includes a neutral density absorber or a quarter wave plate. Laser radiation from a laser diode passes through the neutral density absorber or the quarter wave plate, then passes through the sample cell, and then is incident upon a detector. In some embodiments, the laser diode is driven with a drive current having a stepped periodic waveform.
    Type: Grant
    Filed: December 21, 1994
    Date of Patent: November 21, 2000
    Assignee: Bruce W. McCaul
    Inventors: Bruce W. McCaul, David E. Doggett
  • Patent number: 6150193
    Abstract: A shielded package for an IC chip having bond pads thereon includes an insulating substrate having metallizations formed on a surface of the substrate. The IC chip is mounted to the substrate surface and the IC chip bonding pads are electrically coupled to corresponding substrate metallizations. An insulating encapsulant layer encapsulates the IC chip and the substrate surface. A conductive shield layer comprising a cured flowable electrically conductive material is formed above the encapsulant layer.The encapsulant layer electrically isolates the shield layer from the IC chip and the various electrical conductors (e.g. bonding pads, bond wires, contacts and metallizations). The shield layer, being an electrically conductive material, forms a floating ground plane which shields the IC chip and the remainder of the package.
    Type: Grant
    Filed: May 22, 1998
    Date of Patent: November 21, 2000
    Assignee: Amkor Technology, Inc.
    Inventor: Thomas P. Glenn
  • Patent number: 6148390
    Abstract: A programmable logic device having redundant sets of logic blocks which are capable of being enabled or disabled. The programmable logic device includes a plurality of sets of logic blocks, a plurality of routing resources and a programming circuit. Good logic blocks are enabled and fully operational when programmed. Nonfunctional logic blocks are disabled, powered off and invisible to the programming software. Each set of logic blocks has a corresponding routing resource. The routing resource corresponding to an enabled set of logic blocks is capable of being configured to provide input and output data paths for the enabled set of logic blocks. The routing resource corresponding to a disabled set of logic blocks is capable of being configured to bypass the disabled set of the logic blocks. The programming circuit stores the configuration data for the routing resources and is capable of providing the configuration data to a routing resource that corresponds to an enabled set of logic blocks.
    Type: Grant
    Filed: June 12, 1996
    Date of Patent: November 14, 2000
    Assignee: QuickLogic Corporation
    Inventors: James MacArthur, Timothy M. Lacey
  • Patent number: 6147552
    Abstract: An improved chopper stabilized operational amplifier is disclosed, along with an improved method of timing the switchings of chopper switches in such an amplifier. The disclosure includes an integrated circuit and method for generating a true random voltage signal having a truly random RMS voltage value within a selected range. The true random voltage signal is obtained by amplifying and bandpass filtering random white noise voltages generated by a component of the circuit. The white noise voltages include shot noise voltages generated by bipolar transistors in an input amplifier stage. The random signal generator circuit and method is employed with an oscillator to form a random clock signal generator on the integrated circuit chip. The amount of time between each clocking pulse output by the random clock signal generator truly randomly varies within a selected range of time, and repeats only by random chance.
    Type: Grant
    Filed: October 27, 1998
    Date of Patent: November 14, 2000
    Assignee: National Semiconductor Corporation
    Inventor: Don Roy Sauer
  • Patent number: 6147515
    Abstract: A receiver is provided which quickly and efficiently recognizes signals by including with the receiver a resolving circuit which is coupled to a node control circuit which determines the signals to be recognized. The resolving circuit can operate with supply voltage levels as low as one threshold voltage. Also, the signal hold time can be made very small depending on the sizing of certain transistors. Other advantages include reduced power consumption, high speed operation, good rejection of input noise and power supply noise, ability to resolve small (e.g., 1.0 mVolt) voltage differences, and the ability to function with a variety of types of drivers, including HSTL, DTL and PECL.
    Type: Grant
    Filed: August 3, 1999
    Date of Patent: November 14, 2000
    Assignee: Sun Microsystems, Inc.
    Inventors: Michael A. Ang, Alexander D. Taylor, Jonathan E. Starr
  • Patent number: 6146249
    Abstract: The present invention relates to an apparatus and method of Chemical Mechanical Planarization ("CMP") for wafer, flat panel display (FPD), and hard drive disk (HDD). The preferred apparatus comprises a looped belt spatially oriented in a vertical direction with respect to a ground floor. A polishing pad is glued to an outer surface of the belt. At an inner surface of the belt, there are a plurality of wafer supports to support the wafers while they are in polishing process. Wafers are loaded from a wafer station to a wafer head using a handling structure before polishing and are unloaded from the wafer head to the wafer station after polishing. An electric motor or equivalent is used to drive the looped belt running over two pulleys. An adjustment means is used to adjust the tension and position of the belt for smooth running. This new CMP machine can be mounted in multiple orientations to save manufacturing space.
    Type: Grant
    Filed: October 22, 1998
    Date of Patent: November 14, 2000
    Assignee: Aplex, Inc.
    Inventors: Albert Hu, Burford J. Furman, Mohamed Abushaban