Abstract: This invention provides methods for modulating gene expression at the transcriptional level. In particular, the methods involve tethering a transcriptional coactivator to a DNA binding domain that is specific for a target nucleic acid sequence and contacting the coactivator with a transcription factor. The transcription factor triggers or represses transcription mediated by the coactivator. Methods for identifying compounds that are able to modulate gene expression are also provided.

Abstract: A structure and method for holding a susceptor in a single-wafer RF heated CVD reactor allows the center portion of the susceptor to be heated and prevents susceptor and reactor damage due to overdriving and the susceptor from losing contact with a rotatable rod during thermal expansion. A plug, located on the bottom surface of the susceptor, heated by RF energy subsequently heats the center portion of the susceptor, thereby providing constant temperature gradients across the susceptor. The plug is connected to a rod which is contained in an upper tube and extends into a lower tube. The upper tube is connected to the susceptor via a locking mechanism. An upper spring in the upper tube applies a downward force on the upper tube such that an upward force on the bottom of the susceptor compresses the upper spring, thereby relieving stress on the susceptor and preventing damage due to overdriving.

Abstract: Molecular Complexes, comprising of S-(+)-adenosylmethionine and 3'-azido-2',3'-dideoxy nucleosides are prepared, and shown to have synergistic inhibitory effects on the replication of human-immunodeficiency virus 1 & 2 in vitro and in vivo, particularly on the reverse transcriptase, and having a high therapeutic index.

Abstract: A vehicle masking material and method of use. The masking material in one embodiment includes a dextrin, a plasticizer, and water. The masking material may additionally include a surfactant. The masking material is applied to a surface which is to be protected from paint overspray or other coating processes, allowed to dry, and the surface is coated (e.g. with paint). After drying of the paint, or other coating, the masking material is removed by water washing.

Abstract: Method and apparatus for removing dust produced by the treating of human or animal nails. An air current produced by a fan is directed through an adjustable conduit towards the nails being treated. A funnel attached to a second adjustable conduit leading to a filter is positioned beyond the nails so that dust particles are entrained by the air current and carried into the funnel and to the filter. The fan is of sufficient power to cause very fine dust particles to be removed.

Abstract: Reduction in the net charge at the interface of a dielectric and a semiconductor material is achieved by placing atomic species in the dielectric near the interface. Preferably, these species are selected from the group of alkaline earth metals. The presence of these atoms results in a redistribution of the electronic density near the interface. The placement of the atoms is effected by ion implantation followed by multiple annealing steps at alternating low and high temperatures.

Abstract: A package for an integrated circuit is described, as are methods of making the package. The package includes a substrate having a generally planar first surface on which a metal die pad is formed. An integrated circuit die is attached to the metal die pad. An adhesive head surrounds the integrated circuit die and covers the exposed periphery of the metal die pad. A generally planar lid is in a press-fitted interconnection with the bead. An adhesive material covers conductive structures on the die, such as bonding pads, to prevent corrosion. Optionally, the package has vertical peripheral sides. The methods of making the package include methods for making packages individually, or making a plurality of packages simultaneously. Where a plurality of packages are made simultaneously, integrated circuit die are placed on each of a plurality of physically-joined package substrates on a generally planar sheet of substrate material. An adhesive bead is applied around each die.

Abstract: A split-gate MOS transistor includes two separate but partially overlapping gates to reduce the electric field near the drain-channel interface region and, thereby, has an increased gated-diode breakdown voltage.

Abstract: A molded plastic package incorporates a lead frame which includes a plurality of leads radially aligned around a central opening. A die is mounted in the central opening and is electrically connected to the leads by wire bonding. A molded plastic casing is formed over the die, wiring and lead frame to encapsulate the package. The lower surfaces of the die and lead frame are exposed through the package. A method for making the molded plastic package includes mounting the die and lead frame onto an adhesive tape, electrically connecting the die to the leads by wire bonding, forming a molded plastic casing over the die, wire bonding and lead frame, and then removing the adhesive tape to expose the lower surfaces of the die and the lead frame.

Abstract: In a programmable integrated circuit, by providing a static random access memory (SRAM) cell in each electrically erasable (E.sup.2) non-volatile memory cell, testing time of circuits configured by the E.sup.2 non-volatile memory cells can be reduced substantially. In one embodiment, the SRAM cell can be included by providing a small number of transistors to recirculate the output value of an inverting buffer. During testing, a logic value is written into the SRAM cell in place of the logic value in the non-volatile storage of the E.sup.2 non-volatile memory cell. In one embodiment, the E.sup.2 non-volatile memory cell can be used in conjunction with a 1-bit shift-register. Multiple 1-bit shift registers can be used as a scan chain to scan into the SRAM cells of multiple E.sup.2 non-volatile memory cells.

Abstract: Data are pushed from a source to a destination via an intermediate computer system. If the intermediate computer system is unable to forward the pushed data to the destination for a predetermined length of time, the intermediate system deletes the pushed data and never forwards the data to the destination. According to another aspect, the intermediate system receives a command, e.g. from a server originating the data, to delete the data if the data has not yet been forwarded to the destination. According to another aspect, the intermediate system receives data whose identifier (e.g. source URL) matches an identifier of data pushed earlier to the same destination but not yet forwarded. The intermediate system deletes the earlier pushed data and never forwards the earlier pushed data.

Abstract: A probability analysis technique is performed on magnetically obtained current data to detect short circuit defects in a plate structure (10) in which a group of first electrical conductors (32) are nominally electrically insulated from and cross a group of second electrical conductors (48). In particular, a magnetic current-sensing operation is performed on at least part of the conductors to produce current data indicative of how much, if any, current flows through each of at least part of the conductors. A short circuit defect probability analysis is then applied to the current data in order to select a location where one of the first conductors crosses one of the second conductors as being most probable of having a short circuit defect.

Abstract: A CVD reactor includes separate reaction and pressure chambers, where the reaction chamber is contained within and isolates process or reactant gases from the pressure chamber. The reactor also includes a gas injection system which pre-heats and injects diffused process gas(es) into the reaction chamber in a somewhat vertical direction through a bottom surface of the reaction chamber. The gas injection system injects hydrogen or other appropriate gas in a vertical direction through the bottom surface of the reaction chamber. The flow of hydrogen or other appropriate gas is intermediate the flow of the process gas(es) and a surface of the reaction chamber, thereby re-directing the process gas flow parallel to the top surface of a wafer therein. In this manner, the reaction chamber does not require a long entry length for the process gas(es). This flow of hydrogen or other suitable gas also minimizes undesirable deposition on the surface of the reaction chamber.

Abstract: A 100Base-TX detection system is presented which takes advantage of the form of the frequency response of the channel to provide a simplified filter for producing an output signal with reduced distortion. Utilizing the nature of the frequency response function of category-5 twisted pair cabling, a finite impulse response linear equalizer or an infinite impulse response decision feedback equalizer having as few as two multipliers is implemented.

Abstract: Holographic optical elements (HOEs) can be used in systems and methods for providing illumination and for projecting images. The HOEs may be switchable HOEs, whose diffractive properties can be controlled. Described herein is a method of combining light from two or more illumination sources. In one embodiment, a reflection-type HOE is illuminated by the first illumination source. The HOE diffracts light from the first illumination source into an output direction. Light from the second illumination source is transmitted through the HOE and onto a reflective optical element, which reflects the light back through the HOE and into the same output direction. Also described is a projection system that uses two or more HOEs to combine two or more colors of light for use by a single image display. The system includes one or more light sources, an image display (such as a reflective or transmissive LCD display or a MEMS display, for example), and a first and a second HOE.

Abstract: A polysilicon-based floating gate is formed so as to be resistant to oxidation that occurs during multiple thermo-cycles in fabrication. Accordingly, edge erase times in NOR-type memory devices may be minimized. Additionally, manufacture of oxidation resistant floating gates reduces variations in edge erase times among multiple NOR-type memory devices. A layer of amorphous silicon is deposited over a silicon substrate by directing a mixture of silane and a phosphene-helium gas mixture at the surface of the silicon substrate. Later, N+ ions are implanted into the amorphous silicon. The amorphous silicon layer is then etched so as to overlap slightly with regions that will later correspond to the source and drain regions. Next, a lower oxide layer of an ONO dielectric is deposited and the device is heated. A thermo-cycle is eliminated by heating the amorphous silicon during formation of the oxide layer rather than immediately following its deposition.

Abstract: A circuit and method are provided for disabling a defective normal element using a flip-flop. The flip-flop has two states. In a first state, to which the flip-flop can be set on application of power, the flip-flop enables a normal decoder, corresponding to the normal element, to respond to a respective address for the normal element. In a second state, to which the flip-flop can be set only upon coincident selection of a defective normal element and a programmed redundant element during an initialization routine, the flip-flop disables the normal decoder from responding to any address.

Abstract: An internal supply generator includes a charge pump, at least one regulator and a pump controller. The charge pump generates a charge pump signal whose voltage is higher than an input supply voltage. Each regulator produces a generally stable internal supply from the charge pump signal. The pump controller activates the charge pump whenever the charge pump signal falls to within a predetermined voltage of the voltage level of one of the internal supplies.