Patents Represented by Attorney, Agent or Law Firm Skjerven, Morrill, MacPherson Franklin and Friel
  • Patent number: 6113045
    Abstract: A fitting includes a positioning plate and a holding member connected to the positioning plate by an elongate mounting post. The positioning plate has an outer major wall to serve as a faceplate, and a bore extending from a central area of the outer major wall in an axial direction towards an upright wall, and having inner distal and proximate annular walls fixed on the upright wall by a screw fastener. The mounting post has a mounting portion threadedly engaging the inner distal annular wall, an opposite guiding portion, and an anchoring portion therebetween. The holding member has an axial hole to receive rotatably the guiding and anchoring portions, a skirt portion for concealing the anchoring portion, and a holding portion for holding a support member. A fastening member fixes the holding member relative to the anchoring portion by tightening along a radial direction relative to the axial direction. By means of the mounting post, the holding member is connected to the positioning plate firmly.
    Type: Grant
    Filed: January 20, 1999
    Date of Patent: September 5, 2000
    Inventor: Kuo-Yung Kuo
  • Patent number: 6113708
    Abstract: A component (10 or 12) of a flat-panel display is cleaned with a fluid having a mole-fraction dominant constituent. The cleaning operation is performed by subjecting the component to the cleaning fluid while its absolute pressure exceeds the absolute pressure at the triple point of the dominant constituent and is at least 20% of the absolute pressure value at the critical point of the dominant constituent. The temperature and pressure of the cleaning fluid are typically controlled in a direction toward the supercritical state of the dominant constituent.
    Type: Grant
    Filed: May 26, 1998
    Date of Patent: September 5, 2000
    Assignees: Candescent Technologies Corporation, Hewlett-Packard Company
    Inventors: George B. Hopple, Scott J. Crane, Bob L. Mackey, John D. Porter
  • Patent number: 6115320
    Abstract: A memory system including a memory array, an input circuit and a logic circuit is presented. The input circuit is coupled to receive a memory address and a set of individual write controls for each byte of data word. During a write operation, the input circuit also receives the corresponding write data to be written into the SRAM. The logic circuit causes the write data and write control information to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into memory during a subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers.
    Type: Grant
    Filed: February 23, 1998
    Date of Patent: September 5, 2000
    Assignee: Integrated Device Technology, Inc.
    Inventors: John R. Mick, Mark W. Baumann
  • Patent number: 6115586
    Abstract: A radio frequency synthesizer receives a relatively low frequency input signal and synthesizes from it a high frequency output signal whose frequency can be programmed to change in fine steps, for use e.g. in cordless telephone. The frequency synthesizer includes three linked phase locked loops with a single side band mixer in one embodiment coupling two of the phase locked loops together. This provides an output signal free of in-band frequency spurs within the spacing of two channels. The synthesizer can be integrated in a single chip with a narrowband FM modulation circuit. In spite of using a novel synthesizer to achieve monolithic integration, the user programming interface and control value equations are the industry standard format.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: September 5, 2000
    Assignee: Integrated Circuit Systems, Inc.
    Inventors: Ignatius Bezzam, Herbe Q. H Chun, Gregory Richmond
  • Patent number: 6114217
    Abstract: Disclosed is a method for providing an insulation trench on a semiconductor substrate. The method includes the steps of depositing a pad oxide layer and a nitride layer on a semiconductor substrate; etching the nitride layer and the pad oxide layer and depositing a first insulating layer; forming spacers along sidewalls of the pad oxide layer and the nitride layer by anisotropic etching the first insulating layer; forming trenches by etching the semiconductor substrate; forming a trench insulating layer pattern by depositing a second insulating layer and etching the same; and polishing the trench insulating layer pattern.
    Type: Grant
    Filed: November 24, 1998
    Date of Patent: September 5, 2000
    Assignees: ANAM Semiconductor Inc., Amkor Technology Inc.
    Inventor: Young-Tack Park
  • Patent number: 6108833
    Abstract: A bi-fold futon frame includes force spreading mortise plates positioned at a junction between various wooden members. The mortise plates and the wooden memebers are held together by fasteners such as screws. The wooden members form the frame of the futon.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: August 29, 2000
    Assignee: Elite Furniture, Inc.
    Inventors: Joel Grossman, Justin A. Kumar
  • Patent number: 6111747
    Abstract: An apparatus for securing a board in a connected position includes at least a first edge and a second edge, the apparatus including at least a first retention arm capable of holding in a connected position a first edge of the board, wherein the board is chosen from a plurality of circuit board cards, a heatsink thermal plate coupled to a circuit board card, and a heatsink thermal plate. A computer system includes at least one processor; a memory coupled to the processor and an apparatus for securing a board in a connected position, the device having at least a first edge and a second edge, the apparatus having at least a first retention arm capable of holding in a connected position a first edge of the board, wherein the board is chosen from a plurality of circuit board cards, a heatsink thermal plate coupled to a circuit board card, and a heatsink thermal plate.
    Type: Grant
    Filed: October 19, 1998
    Date of Patent: August 29, 2000
    Assignee: Dell USA, L.P.
    Inventors: John Jeffries, Stephen Cook
  • Patent number: 6109994
    Abstract: Portions (40 and 44) of a structure, such as a flat-panel device, are sealed together by a gap-jumping technique in which a sealing area (40S) of one portion is positioned near a matching sealing area (44S) of another portion such that a gap (48) at least partially separates the two sealing areas. The gap typically has an average height of 25 .mu.m or more. With the two portions of the structure so positioned, energy is initially transferred locally to material of a specified one of the portions along part of the gap while the two portions are in a non-vacuum environment to cause material of the two portions to bridge that part of the gap and partially seal the two portions together along the sealing areas.
    Type: Grant
    Filed: December 12, 1996
    Date of Patent: August 29, 2000
    Assignee: Candescent Technologies Corporation
    Inventors: Steven T. Cho, Alfred S. Conte, Paul N. Ludwig, Anthony P. Schmid, Theodore S. Fahlen, Robert J. Pressley
  • Patent number: 6110040
    Abstract: A video poker gaming machine is described where, after initially dealing five cards to a player, the machine displays a sixth card to replace a discarded card by the player. In one embodiment, the sixth card automatically replaces the leftmost discarded card. In another embodiment, the sixth card can replace any of the discarded cards.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: August 29, 2000
    Assignee: Sigma Game Inc.
    Inventors: Thomas J. Sanduski, Robert J. Piechowiak
  • Patent number: 6112325
    Abstract: Device for determining the rate of a received communication frame, including a plurality of encoded signal quality estimators, each at a different rate, a decision controller, connected to the encoded signal quality estimators, a decoder connected to the controller and an erasure detection unit connected to the decoder and the controller, wherein each of the quality estimators processes the received encoded frame according to an encoded signal quality criteria, thereby producing a quality value, wherein the controller selects the rate with the best quality value, the decoder decodes the encoded frame according to the selected rate and the erasure detection unit analyzing the decoded frame, thereby determining it as allowed or as erased.
    Type: Grant
    Filed: January 23, 1998
    Date of Patent: August 29, 2000
    Assignee: DSPC Technologies, Ltd.
    Inventor: David Burshtein
  • Patent number: 6111199
    Abstract: An integrated circuit package includes a number of electrical conductors that are completely or at least partially surrounded by a gas instead of a solid material (having no cavities) used in the prior art. Such use of a gas reduces the dielectric constant in a region around each of the electrical conductors, as compared to the dielectric constant of a solid dielectric material. In one implementation, a number of leads are kept separated from a substrate by a number of electrically conductive support members attached to the substrate. Each lead is electrically coupled (e.g. by a bond wire) to a die pad on a die that is supported by the package in the normal manner. The leads are initially formed as portions of a lead frame (e.g. by etching or stamping), and are held separate from each other by the respective support members. The support members are electrically coupled (e.g. by traces and vias in the substrate) to terminals (e.g. pins, balls or lands) of the package.
    Type: Grant
    Filed: April 7, 1998
    Date of Patent: August 29, 2000
    Assignee: Integrated Device Technology, Inc.
    Inventors: Christopher P. Wyland, Richard L. Guilhamet
  • Patent number: 6110346
    Abstract: In electroplating a metal layer on a semiconductor wafer, the resistive voltage drop between the edge of the wafer, where the electrical terminal is located, and center of the wafer causes the plating rate to be greater at the edge than at the center. As a result of this so-called "terminal effect", the plated layer tends to be concave. This problem is overcome by first setting the current at a relatively low level until the plated layer is sufficiently thick that the resistive drop is negligible, and then increasing the current to improve the plating rate. Alternatively, the portion of the layer produced at the higher current can be made slightly convex to compensate for the concave shape of the portion of the layer produced at the lower current. This is done by reducing the mass transfer of the electroplating solution near the edge of the wafer to the point that the electroplating process is mass transfer limited in that region.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: August 29, 2000
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan D. Reid, Robert J. Contolini, Edward C. Opocensky, Evan E. Patton, Eliot K. Broadbent
  • Patent number: 6112266
    Abstract: An HSP communication system includes a host computer which executes a software portion of an HSP modem and a device containing a digital-to-analog converter (DAC). In response to interrupts, the host executes an update routine that generates and writes samples to a software circular buffer in memory of the host computer. The samples represent amplitudes of an analog signal complying with a desired communication protocol. A direct transfer moves samples from the software circular buffer to a hardware circular buffer the device, and the DAC converts the samples from the hardware circular buffer into an analog communication signal. In an exemplary embodiment, the hardware portion is coupled to a PCI bus in the host computer, and direct transfers are according to the PCI bus master protocol. In environments such as multi-tasking systems, the host may skip interrupts or otherwise not provide new samples when required.
    Type: Grant
    Filed: January 22, 1998
    Date of Patent: August 29, 2000
    Assignee: PC-Tel, Inc.
    Inventor: Han C. Yeh
  • Patent number: 6111324
    Abstract: A carrier ring provides a stiffening function for assembling flexible circuits or semi-rigid circuits. The carrier ring is attached to a substrate adapted for attachment of a matrix of semiconductor dies. The carrier ring is provided with mold gates and mold vents for use with a transfer molding step to provide encapsulation for the semiconductor dies. Alignment and indexing marks on the carrier ring allows use of conventional assembly process flows in conventional assembly equipment. The height of the carrier ring also provides a means of providing integrated circuits with a predetermined thickness.
    Type: Grant
    Filed: February 5, 1998
    Date of Patent: August 29, 2000
    Assignee: ASAT, Limited
    Inventors: Robert P. Sheppard, Edward G. Combs
  • Patent number: 6110395
    Abstract: The present invention relates to a method and structure for controlling plasma uniformity in plasma processing applications. Electron thermal conductivity parallel and perpendicular to magnetic field lines differs by orders of magnitude for low magnetic fields (on the order of 10 gauss). This property allows the directing of heat flux by controlling the magnetic field configuration independent of ions since the effect of modest magnetic fields upon the transport of ions themselves is minimal. Heat is preferentially conducted along magnetic field lines with electron temperatures on the order of 0.1 to 1 eV/cm being sufficient to drive kilowatt-level heat fluxes across areas typical of plasma processing source dimensions.
    Type: Grant
    Filed: August 26, 1997
    Date of Patent: August 29, 2000
    Assignee: Trikon Technologies, Inc.
    Inventor: Gerald W. Gibson, Jr.
  • Patent number: 6107728
    Abstract: An electrode (12 or 30) of an electron-emitting device has a plurality of openings (16 or 60) spaced laterally apart from one another. The openings can be used, as needed, in selectively separating one or more parts of the electrode from the remainder of the electrode during corrective test directed towards repairing any short-circuit defects that may exist between the electrode and other overlying or underlying electrodes. When the electrode with the openings is an emitter electrode (12), each opening (16) normally extends fully across an overlying control electrode (30). When the electrode with the openings is a control electrode (30), each opening (60) normally extends fully across an underlying emitter electrode (12). The short-circuit repair procedure typically entails directing light energy on appropriate portions of the electrode with the openings.
    Type: Grant
    Filed: April 30, 1998
    Date of Patent: August 22, 2000
    Assignee: Candescent Technologies Corporation
    Inventors: Christopher J. Spindt, John E. Field, Theodore S. Fahlen
  • Patent number: 6107806
    Abstract: A device (16) for sensing current flowing in a generally flat plate structure (10) contains a magnetic head (18) and signal processing circuitry (20). The magnetic head (a) senses changes in current-induced magnetic flux as the head is positioned over the plate structure and (b) provides a head output signal. The signal processing circuitry processes the head output signal to produce a data signal indicative of how much current appears to flow in the plate structure below the head. A driving voltage, which typically varies in a periodic manner to produce a characteristic signature, is applied to a primary conductor in the plate structure. A location sensor, typically formed with a light source (100) and a light sensor (102), detects the position of the magnetic head relative to the plate structure. A gas-cushion mechanism (80-98) controls the height of the head above the plate structure.
    Type: Grant
    Filed: July 30, 1997
    Date of Patent: August 22, 2000
    Assignee: Candescent Technologies Corporation
    Inventor: John E. Field
  • Patent number: 6106565
    Abstract: A development system includes two processors which can each act as the central processing unit of the development system. Control is passed between the processors via a system management mode (SMM) interrupt under the X86 architecture. In one embodiment, one of the processor is a processor to be emulated and the other processor is an emulating processor. Since the emulating processor runs at a much slower clock speed than the emulated processor, an application program can be run by the emulating processor until a region of interest is reached. The control of the application program can then be transferred by the SMM interrupt to the emulated processor. This arrangement allows a new compatible microprocessor to be efficiently developed using a hardware emulation system.
    Type: Grant
    Filed: February 27, 1997
    Date of Patent: August 22, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Warren Stapleton, Keith R. Shakel, Fred C. Jair, Jennifer B. Pencis, Mrityunjay R. Hiremath
  • Patent number: 6108215
    Abstract: An inverter circuit having dual converters for driving a fluorescent lamp comprising a pulse width modulator coupled to receive a feedback signal indicative of current in the fluorescent lamp. The pulse width modulator generates driving signals that are received by a synchronously switching voltage regulator having a high side driver and a low side driver. A self-resonant converter is coupled between the synchronously switching voltage regulator and the fluorescent lamp and generates a voltage signal for illuminating the fluorescent lamp. The self-resonant converter includes a transformer having a primary winding and at least one secondary winding, a capacitor coupled in parallel with the primary winding, and a full bridge circuit. The full bridge circuit may include four switching transistors, such as MOSFETs coupled in an H-configuration to the primary winding and the capacitor.
    Type: Grant
    Filed: January 22, 1999
    Date of Patent: August 22, 2000
    Assignee: Dell Computer Corporation
    Inventors: Barry K. Kates, John Cummings
  • Patent number: 6107873
    Abstract: A preamplifier circuit couple to a magneto-resistive (MR) head used in the read circuitry of a magnetic storage device includes differential amplifiers coupled to receive an input from the MR head and to provide output signals. The preamplifier is designed to provide a low noise level. To minimize noise, transistors of the differential amplifiers provide high current gain and have large device geometries.
    Type: Grant
    Filed: March 30, 1998
    Date of Patent: August 22, 2000
    Assignee: National Semiconductor Corporation
    Inventor: Perry Scott Lorenz